ATA6612P-PLPW Atmel, ATA6612P-PLPW Datasheet - Page 215
ATA6612P-PLPW
Manufacturer Part Number
ATA6612P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.17.9.4
9111H–AUTO–01/11
USART Control and Status Register n C – UCSRnC
Table 6-74.
Note:
Table 6-75.
Initial Value
Read/Write
• Bit 2 – UCSZn2: Character Size n
• Bit 1 – RXB8n: Receive Data Bit 8 n
• Bit 0 – TXB8n: Transmit Data Bit 8 n
• Bits 7:6 – UMSELn1:0 USART Mode Select
• Bits 5:4 – UPMn1:0: Parity Mode
• Bit 3 – USBSn: Stop Bit Select
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data
bits (Character SiZe) in a frame the Receiver and Transmitter use.
RXB8n is the ninth data bit of the received character when operating with serial frames
with nine data bits. Must be read before reading the low bits from UDRn.
TXB8n is the ninth data bit in the character to be transmitted when operating with serial
frames with nine data bits. Must be written before writing the low bits to UDRn.
These bits select the mode of operation of the USARTn as shown in
These bits enable and set type of parity generation and check. If enabled, the Transmitter
will automatically generate and send the parity of the transmitted data bits within each
frame. The Receiver will generate a parity value for the incoming data and compare it to
the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver
ignores this setting.
Bit
UMSELn1
UPMn1
1. See
0
0
1
1
0
0
1
1
operation
UMSELn1
R/W
UMSELn Bits Settings
UPMn Bits Settings
“USART in SPI Mode” on page 220
7
0
UMSELn0
R/W
6
0
UMSELn0
UPMn0
0
1
0
1
0
1
0
1
UPMn1
R/W
5
0
UPMn0
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
R/W
Mode
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)
4
0
Atmel ATA6612/ATA6613
for full description of the Master SPI Mode (MSPIM)
USBSn
R/W
3
0
UCSZn1
R/W
2
1
(1)
UCSZn0
R/W
1
1
Table
UCPOLn
R/W
6-74.
0
0
UCSRnC
215
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