ATTINY861-20MU Atmel, ATTINY861-20MU Datasheet - Page 107

• Manufacturer Part Number: ATTINY861-20MU
• Description: IC MCU AVR 8K FLASH 20MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY861-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.10 Fault Protection Unit
2588E–AVR–08/10
Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 12-18
Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (f
The Timer/Counter1 incorporates a Fault Protection unit, which can be set to disable the PWM
output pins when an external event is triggered. The external signal indicating an event can be
applied via the external interrupt INT0 pin or, alternatively, via the analog-comparator unit. The
Fault Protection unit is illustrated in
directly a part of the Fault Protection unit are gray shaded.
Figure 12-19. Fault Protection Unit Block Diagram
Fault Protection mode is enabled by setting the Fault Protection Enable (FPEN1) bit and trig-
gered by a change in logic level at external interrupt pin (INT0). Alternatively, fault protection
mode can be triggered by the Analog Comparator Output (ACO).
When Fault Protection is triggered, the COM1x bits are cleared, Output Comparators are discon-
nected from the PWM output pins and PORTB register bits are connected to the PWM output
TCNTn
(clk
TCNTn
OCRnx
(clk
OCFnx
TOVn
clk
clk
clk
INT0
clk
PCK
PCK
PCK
Tn
PCK
Tn
/8)
/8)
Comparator
shows the setting of TOV1 in Phase and Frequency Correct PWM Mode.
Analog
ACO*
BOTTOM + 1
OCRnx - 1
FPAC1
Figure
Canceler
FPNC1
Noise
BOTTOM + 1
12-19. The elements of the block diagram that are not
OCRnx
OCRnx Value
FPES1
Detector
Edge
FPEN1
OCRnx + 1
clkT1
BOTTOM
/8)
FAULT_PROTECTION (Int. Req.)
Timer/Counter1
BOTTOM + 1
clkT1
OCRnx + 2
/8)
107