PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 281

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 23-1:
REGISTER 23-2:
© 2006 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4-1
bit 0
bit 7-3
bit 2
bit 1-0
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
bit 7
Unimplemented: Read as ‘0’
CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
Unimplemented: Read as ‘0’
bit 7
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
Legend:
R = Readable bit
-n = Value when device is unprogrammed
Legend:
R = Readable bit
-n = Value when device is unprogrammed
R/WO-1
DEBUG
Note 1: This bit should always be maintained as ‘0’.
U-0
—
R/WO-1
XINST
U-0
—
STVREN
R/WO-1
WO = Write-once bit
WO = Write-once bit
U-0
Preliminary
—
U-0
U-0
—
—
—
U-0
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
U-0
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
—
(1)
PIC18F87J10
R/WO-1
CP0
U-0
—
‘0’ = Bit is cleared
‘0’ = Bit is cleared
U-0
U-0
DS39663D-page 279
—
—
WDTEN
R/WO-1
U-0
—
bit 0
bit 0