PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 372

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10
FIGURE 26-13:
TABLE 26-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
DS39663D-page 370
Param
70
71
71A
72
72A
73A
74
75
76
77
78
79
80
82
83
Note 1:
No.
Note:
(CKP = 0)
(CKP = 1)
SDI
SDIx
SCKx
SDOx
SSx
SCKx
2:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SS
SS
SC
SC
SC
SC
SS
SC
SC
SC
SC
SS
SC
SC
Symbol
B
DO
DO
2
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
L2
L2
H2
H2
L2
L2
H2
L2
Refer to Figure 26-2 for load conditions.
H
L
H2
L2
R
F
B
R
F
DO
DO
SS
SC
SC
DI
DO
DO
SS
DI
L
H
L,
H,
L
V
V SDOx Data Output Valid after SSx
H,
V,
Z SSx
SSx
SCKx Input High Time
(Slave mode)
SCKx Input Low Time
(Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDIx Data Input to SCKx Edge
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
SDOx Data Output Valid after SCKx Edge
SSx
82
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
70
to SCKx
to SDOx Output High-Impedance
after SCKx Edge
MSb In
MSb
74
71
or SCKx
75, 76
Characteristic
72
bit 6 - - - - - - 1
bit 6 - - - - 1
Input
Preliminary
Continuous
Single Byte
Continuous
Single Byte
Edge
80
LSb
LSb In
1.25 T
1.25 T
1.5 T
Min
T
100
CY
40
40
CY
10
—
—
—
—
—
—
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
© 2006 Microchip Technology Inc.
77
Max Units Conditions
25
25
50
25
25
50
50
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)