PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 364

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10
FIGURE 26-5:
TABLE 26-10: CLKO AND I/O TIMING REQUIREMENTS
DS39663D-page 362
150
151
155
160
161
162
163
164
165
166
167
168
169
171
171A
Param.
Operating Conditions: 2.0V < V
AD<15:0>
No
A<19:16>
OSC1
BA0
ALE
CE
OE
TadV2alL
TalL2adl
TalL2oeL
TadZ2oeL
ToeH2adD OE
TadV2oeH LS Data Valid before OE
ToeH2adl
TalH2alL
ToeL2oeH OE Pulse Width
TalH2alH
Tacc
Toe
TalL2oeH
TalH2csL
TubL2oeH AD Valid to Chip Enable Active
Symbol
Address Out Valid to ALE
(address setup time)
ALE
(address hold time)
ALE
AD high-Z to OE
OE
ALE Pulse Width
ALE
Address Valid to Data Valid
OE
ALE
Chip Enable Active to ALE
Q1
PROGRAM MEMORY READ TIMING DIAGRAM
to AD Driven
to Data In Invalid (data hold time)
to Data Valid
to Address Out Invalid
to OE
to ALE
to OE
CC
164
Address
< 3.6V, -40°C < T
150
151
Characteristics
171
171A
(cycle time)
Q2
(bus release to OE)
167
A
(data setup time)
155
< +125°C unless otherwise stated.
160
Preliminary
Q3
Address
166
168
169
0.625 T
0.25 T
0.125 T
0.75 T
0.25 T
165
0.5 T
Data from External
Q4
Min
10
20
—
—
—
CY
CY
CY
CY
162
5
0
0
CY
163
CY
– 10
– 5
– 25
– 20
– 10
– 5
0.125 T
0.25 T
0.5 T
161
Typ
T
—
—
—
—
—
—
—
—
—
—
—
© 2006 Microchip Technology Inc.
CY
Q1
CY
CY
CY
0.625 T
0.5 T
Max
Address
Address
CY
10
—
—
—
—
—
—
—
—
—
—
—
—
CY
– 25
+ 10
Q2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns