PIC18F65J10-I/PT Microchip Technology, PIC18F65J10-I/PT Datasheet - Page 388

• Manufacturer Part Number: PIC18F65J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J10-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J10
Calibration (A/D Converter) .............................................. 265
CALL ................................................................................ 304
CALLW ............................................................................. 333
Capture (CCP Module) ..................................................... 167
Capture (ECCP Module) .................................................. 176
Capture/Compare/PWM (CCP) ........................................ 165
Clock Sources .................................................................... 30
CLRF ................................................................................ 305
CLRWDT .......................................................................... 305
Code Examples
Code Protection ............................................................... 277
COMF ............................................................................... 306
Comparator ...................................................................... 267
DS39663D-page 386
MPLAB C18 ............................................................. 340
MPLAB C30 ............................................................. 340
Associated Registers ............................................... 169
CCP Pin Configuration ............................................. 167
CCPRxH:CCPRxL Registers ................................... 167
Prescaler .................................................................. 167
Software Interrupt .................................................... 167
Timer1/Timer3 Mode Selection ................................ 167
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 166
CCPRxH Register .................................................... 166
CCPRxL Register ..................................................... 166
Compare Mode. See Compare.
Module Configuration ............................................... 166
Timer Interconnect Configurations ........................... 166
Default System Clock on Reset ................................. 31
Selection Using OSCCON Register ........................... 31
16 x 16 Signed Multiply Routine .............................. 104
16 x 16 Unsigned Multiply Routine .......................... 104
8 x 8 Signed Multiply Routine .................................. 103
8 x 8 Unsigned Multiply Routine .............................. 103
Changing Between Capture Prescalers ................... 167
Computed GOTO Using an Offset Value ................... 61
Erasing a Flash Program Memory Row ..................... 86
Fast Register Stack .................................................... 61
How to Clear RAM (Bank 1) Using Indirect Addressing .
Implementing a Real-Time Clock Using a Timer1 Inter-
Initializing PORTA .................................................... 122
Initializing PORTB .................................................... 124
Initializing PORTC .................................................... 127
Initializing PORTD .................................................... 130
Initializing PORTE .................................................... 133
Initializing PORTF .................................................... 136
Initializing PORTG ................................................... 138
Initializing PORTH .................................................... 140
Initializing PORTJ .................................................... 142
Loading the SSP1BUF (SSP1SR) Register ............. 192
Reading a Flash Program Memory Word .................. 85
Saving STATUS, WREG and BSR Registers in RAM ...
Writing to Flash Program Memory ............................. 88
Analog Input Connection Considerations ................. 271
Associated Registers ............................................... 271
Configuration ............................................................ 268
Effects of a Reset ..................................................... 270
Interrupts .................................................................. 270
Operation ................................................................. 269
Operation During Sleep ........................................... 270
Outputs .................................................................... 269
Reference ................................................................ 269
74
rupt Service ...................................................... 155
120
Preliminary
Comparator Specifications ............................................... 356
Comparator Voltage Reference ....................................... 273
Compare (CCP Module) .................................................. 168
Compare (ECCP Module) ................................................ 176
Computed GOTO ............................................................... 61
Configuration Bits ............................................................ 277
Configuration Register Protection .................................... 288
Core Features
CPFSEQ .......................................................................... 306
CPFSGT .......................................................................... 307
CPFSLT ........................................................................... 307
Crystal Oscillator/Ceramic Resonator ................................ 27
Customer Change Notification Service ............................ 395
Customer Notification Service ......................................... 395
Customer Support ............................................................ 395
D
Data Addressing Modes .................................................... 74
Data Memory ..................................................................... 64
DAW ................................................................................ 308
DC Characteristics ........................................................... 353
DCFSNZ .......................................................................... 309
DECF ............................................................................... 308
DECFSZ .......................................................................... 309
Default System Clock ........................................................ 31
Response Time ........................................................ 269
Accuracy and Error .................................................. 274
Associated Registers ............................................... 275
Configuring .............................................................. 273
Connection Considerations ...................................... 274
Effects of a Reset .................................................... 274
Operation During Sleep ........................................... 274
Associated Registers ............................................... 169
CCPRx Register ...................................................... 168
Pin Configuration ..................................................... 168
Software Interrupt .................................................... 168
Timer1/Timer3 Mode Selection ................................ 168
Special Event Trigger .............................. 161, 176, 264
Easy Migration ............................................................. 6
Expanded Memory ....................................................... 5
Extended Instruction Set ............................................. 5
External Memory Bus .................................................. 5
nanoWatt Technology .................................................. 5
Oscillator Options and Features .................................. 5
Comparing Addressing Modes with the Extended In-
Direct ......................................................................... 74
Indexed Literal Offset ................................................ 77
Indirect ....................................................................... 74
Inherent and Literal .................................................... 74
Access Bank .............................................................. 67
Bank Select Register (BSR) ...................................... 64
Extended Instruction Set ........................................... 77
General Purpose Registers ....................................... 67
Memory Maps
Special Function Registers ........................................ 68
Power-Down and Supply Current ............................ 346
Supply Voltage ........................................................ 345
External Signal ................................................ 269
Internal Signal .................................................. 269
struction Set Enabled ........................................ 78
BSR ................................................................... 79
Instructions Affected .......................................... 77
Mapping Access Bank ....................................... 79
PIC18FX5J10/X5J15/X6J10 Devices ................ 65
PIC18FX6J15/X7J10 Devices ........................... 66
Special Function Registers ................................ 68
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