PIC18F6490-E/PT Microchip Technology, PIC18F6490-E/PT Datasheet - Page 156

IC PIC MCU FLASH 16KX16 64TQFP

PIC18F6490-E/PT

Manufacturer Part Number
PIC18F6490-E/PT
Description
IC PIC MCU FLASH 16KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F6490-E/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
For Use With
DM163028 - BOARD DEMO PICDEM LCD
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F6490-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6390/6490/8390/8490
14.4.2
The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCP2CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON<5:4> bits contain
the two LSbs. This 10-bit value is represented by
CCPR2L:CCP2CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 14-2:
CCPR2L and CCP2CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only register.
TABLE 14-4:
DS39629C-page 154
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) •
PWM Frequency
PWM DUTY CYCLE
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
T
OSC
• (TMR2 Prescale Value)
2.44 kHz
FFh
16
14
9.77 kHz
FFh
12
4
39.06 kHz
The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR2H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 14-3:
Note:
FFh
10
1
PWM Resolution (max)
If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
156.25 kHz
3Fh
1
8
© 2007 Microchip Technology Inc.
312.50 kHz
=
1Fh
log
-----------------------------bits
1
7
log
---------------
F
F
PWM
2 ( )
OSC
416.67 kHz
6.58
17h
1

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