ATMEGA644A-AUR Atmel, ATMEGA644A-AUR Datasheet - Page 316
ATMEGA644A-AUR
Manufacturer Part Number
ATMEGA644A-AUR
Description
IC MCU AVR 64K FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA644A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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26.10.4
26.10.5
26.10.6
26.10.7
8272A–AVR–01/10
PROG_COMMANDS (0x5)
PROG_PAGELOAD (0x6)
PROG_PAGEREAD (0x7)
Data Registers
The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as Data Register. The active
states are the following:
• Capture-DR: The result of the previous command is loaded into the Data Register.
• Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous
• Update-DR: The programming command is applied to the Flash inputs
• Run-Test/Idle: One clock cycle is generated, executing the applied command
The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs
of the Programming Command Register. The active states are the following:
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
• Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A
The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port.
An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs
of the Programming Command Register. The active states are the following:
• Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte
• Shift-DR: The Flash Data Byte Register is shifted by the TCK input.
The Data Registers are selected by the JTAG instruction registers described in section
gramming Specific JTAG Instructions” on page
programming operations are:
• Reset Register
• Programming Enable Register
• Programming Command Register
• Flash Data Byte Register
164A/164PA/324A/324PA/644A/644PA/1284/1284P
command and shifting in the new command.
write sequence is initiated that within 11 TCK cycles loads the content of the temporary
register into the Flash page buffer. The AVR automatically alternates between writing the low
and the high byte for each new Update-DR state, starting with the low byte for the first Update-
DR encountered after entering the PROG_PAGELOAD command. The Program Counter is
pre-incremented before writing the low byte, except for the first written byte. This ensures that
the first data is written to the address set up by PROG_COMMANDS, and loading the last
location in the page buffer does not make the program counter increment into the next page.
Register. The AVR automatically alternates between reading the low and the high byte for each
new Capture-DR state, starting with the low byte for the first Capture-DR encountered after
entering the PROG_PAGEREAD command. The Program Counter is post-incremented after
reading each high byte, including the first read byte. This ensures that the first data is captured
from the first address set up by PROG_COMMANDS, and reading the last location in the page
makes the program counter increment into the next page.
314. The Data Registers relevant for
”Pro-
316
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