DSPIC33FJ12MC202-I/SS Microchip Technology, DSPIC33FJ12MC202-I/SS Datasheet - Page 269
![IC DSPIC MCU/DSP 12K 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
DSPIC33FJ12MC202-I/SS
Manufacturer Part Number
DSPIC33FJ12MC202-I/SS
Description
IC DSPIC MCU/DSP 12K 28SSOP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SS
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ12MC202-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 269 of 282
- Download datasheet (4Mb)
TABLE 24-1:
© 2008 Microchip Technology Inc.
Section 9.0 “I/O Ports”
Section 13.0 “Output Compare”
Section 14.0 “Motor Control
PWM Module”
Section 15.0 “Quadrature
Encoder Interface (QEI) Module”
Section 16.0 “Serial Peripheral
Interface (SPI)”
Section Name
MAJOR SECTION UPDATES
Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain Configuration”,
which provides details on I/O pins and their functionality.
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 9.4.2 “Available Peripherals”
• 9.4.3.3 “Mapping”
• 9.4.5 “Considerations for Peripheral Pin Selection”
Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with
entirely new content.
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 14.3 “PWM Time Base
• 14.4 “PWM Period”
• 14.5 “Edge-Aligned PWM”
• 14.6 “Center-Aligned PWM”
• 14.7 “PWM Duty Cycle Comparison Units”
• 14.8 “Complementary PWM Operation”
• 14.9 “Dead-Time Generators”
• 14.10 “Independent PWM Output”
• 14.11 “Single Pulse PWM Operation”
• 14.12 “PWM Output Override”
• 14.13 “PWM Output and Polarity Control
• 14.14 “PWM Fault Pins”
• 14.15 “PWM Update Lockout”
• 14.16 “PWM Special Event Trigger”
• 14.17 “PWM Operation During CPU Sleep Mode”
• 14.18 “PWM Operation During CPU Idle Mode
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 15.1 “Quadrature Encoder Interface Logic”
• 15.2 “16-bit Up/Down Position Counter Mode”
• 15.3 “Position Measurement Mode”
• 15.4 “Programmable Digital Noise Filters”
• 15.5 “Alternate 16-bit Timer/Counter”
• 15.6 QEI Module Operation During CPU Sleep Mode”
• 15.7 “QEI Module Operation During CPU Idle Mode”
• 15.8 “Quadrature Encoder Interface Interrupts”
Removed the following sections, which are now available in the related section
of the dsPIC33F Family Reference Manual:
• 16.1 “Interrupts”
• 16.2 “Receive Operations”
• 16.3 “Transmit Operations”
• 16.4 “SPI Setup: Master Mode”
• 16.5 “SPI Setup: Slave Mode” (retained Figure 16-1: SPI Module Block
Diagram)
Preliminary
dsPIC33FJ12MC201/202
Update Description
DS70265C-page 267
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