PIC18F65K90-I/PTRSL Microchip Technology, PIC18F65K90-I/PTRSL Datasheet - Page 110
![MCU PIC 32K FLASH MEM XLP 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/PTRSL
Manufacturer Part Number
PIC18F65K90-I/PTRSL
Description
MCU PIC 32K FLASH MEM XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/PTRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65K90-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K90 FAMILY
FIGURE 7-2:
7.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
7.2.1
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register,
not a physical register, is used exclusively in the
memory
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access is a
program or data EEPROM memory access. When
clear, any subsequent operations operate on the data
EEPROM memory. When set, any subsequent
operations operate on the program memory.
The CFGS control bit determines if the access is to the
Configuration/Calibration registers or to program
memory/data
subsequent operations operate on Configuration
registers regardless of EEPGD (see Section 28.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
DS39957B-page 110
Note 1: The Table Pointer actually points to one of 64 holding registers; the address of which is determined by
Control Registers
TBLPTRU
write
EECON1 AND EECON2 REGISTERS
EEPROM
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
and
Table Pointer
TBLPTRH
TABLE WRITE OPERATION
erase
memory.
(1)
sequences.
TBLPTRL
Program Memory
(TBLPTR)
When
Reading
set,
Preliminary
Instruction:
Holding Registers
Program Memory
The FREE bit, when set, allows a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, allows a write operation. On
power-up, the WREN bit is clear. The WRERR bit is set
in hardware when the WR bit is set and cleared when
the internal programming timer expires and the write
operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the write operation.
TBLWT
Note:
Note:
*
During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
The EEIF interrupt flag bit (PIR6<4>) is set
when the write is complete. It must be
cleared in software.
2010 Microchip Technology Inc.
Table Latch (8-bit)
TABLAT
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