PIC18F65K90-I/PTRSL Microchip Technology, PIC18F65K90-I/PTRSL Datasheet - Page 438
![MCU PIC 32K FLASH MEM XLP 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F65K90-I/PTRSL
Manufacturer Part Number
PIC18F65K90-I/PTRSL
Description
MCU PIC 32K FLASH MEM XLP 64TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F65K90-I/PTRSL
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
2048Byte
Cpu Speed
16MIPS
No. Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F65K90-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K90 FAMILY
28.2
For the PIC18F87K90 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCF bits (OSCCON<6:4>) are
changed or a clock failure has occurred.
FIGURE 28-1:
DS39957B-page 438
WDT Disabled in Hardware,
Change on IRCF<2:0> bits
WDTEN0
WDTEN1
WDT Enabled only While
Device Active, Disabled
WDT Controlled with
SWDTEN bit Setting
SWDTEN Disabled
Watchdog Timer (WDT)
SWDTEN Disabled
All Device Resets
WDT Enabled,
INTRC Source
WDTPS<3:0>
CLRWDT
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
128
Preliminary
4
Programmable Postscaler
1:1 to 1:1,048,576
The WDT can be operated in one of four modes as
determined by CONFIG2H (WDTEN<1:0>) The four
modes are:
• WDT Enabled
• WDT Disabled
• WDT under software control (WDTCON<0>,
• WDT
INTRC Source
SWDTEN)
- Enabled during normal operation
- Disabled during Sleep
WDTEN<1:0>
Note 1: The CLRWDT and SLEEP instructions
SWDTEN
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
Reset
Enable WDT
2010 Microchip Technology Inc.
Wake-up from
Power-Managed
Modes
WDT
Reset
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