PIC18F2580-E/SP Microchip Technology, PIC18F2580-E/SP Datasheet - Page 169

• Manufacturer Part Number: PIC18F2580-E/SP
• Description: IC PIC MCU FLASH 16KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2580-E/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: SPI/I2C/MSSP/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (ECCP1M3:ECCP1M0). At the same time,
the interrupt flag bit ECCP1IF is set.
15.3.1
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
FIGURE 15-2:
© 2007 Microchip Technology Inc.
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2 compare output latch (depending
on device configuration) to the default low
level. This is not the PORTC I/O data
latch.
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
ECCPR1H
TMR1H
TMR3H
CCPR1H
T3CCP1
Comparator
Comparator
ECCPR1L
CCPR1L
TMR1L
TMR3L
Compare
Compare
Match
Match
PIC18F2480/2580/4480/4580
1
0
Set CCP1IF
Preliminary
T3ECCP1
Set CCP1IF
(Timer1/Timer3 Reset, A/D Trigger)
15.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP interrupt is generated, if enabled,
and the CCP1IE bit is set.
15.3.4
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting the
Compare
(CCP1M3:CCP1M0 = 1011).
For either CCP module, the Special Event Trigger
resets the Timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPR1 registers to serve as a
programmable period register for either timer.
Special Event Trigger
Special Event Trigger
ECCP1CON<3:0>
CCP1CON<3:0>
(Timer1 Reset)
Output
Output
Logic
4
Logic
4
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
S
R
Q
Q
Event
Output Enable
Output Enable
TRIS
TRIS
DS39637C-page 167
Trigger
ECCP1 pin
CCP1 pin
mode