PIC18F8390-I/PT Microchip Technology, PIC18F8390-I/PT Datasheet - Page 399
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F8390-I/PT
Manufacturer Part Number
PIC18F8390-I/PT
Description
IC PIC MCU FLASH 4KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6310-IPT.pdf
(28 pages)
3.PIC18F6390-IPT.pdf
(414 pages)
4.PIC18F6390-IPT.pdf
(16 pages)
5.PIC18F6390-IPT.pdf
(12 pages)
6.PIC18F6390-IPT.pdf
(6 pages)
7.PIC18F6390-IPT.pdf
(4 pages)
8.PIC18F8490-IPT.pdf
(412 pages)
Specifications of PIC18F8390-I/PT
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
Number Of I /o
66
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8390-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8390-I/PT
Manufacturer:
MICRO
Quantity:
20 000
INDEX
A
A/D ................................................................................... 231
Absolute Maximum Ratings ............................................. 351
AC (Timing) Characteristics ............................................. 368
Access Bank ...................................................................... 73
ACKSTAT ........................................................................ 187
ACKSTAT Status Flag ..................................................... 187
ADCON0 Register ............................................................ 231
ADCON1 Register ............................................................ 231
ADCON2 Register ............................................................ 231
ADDFSR .......................................................................... 338
ADDLW ............................................................................ 301
Addressable Universal Synchronous
ADDULNK ........................................................................ 338
ADDWF ............................................................................ 301
ADDWFC ......................................................................... 302
ADRESH Register ............................................................ 231
ADRESL Register .................................................... 231, 234
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 302
ANDWF ............................................................................ 303
Assembler
AUSART
2004 Microchip Technology Inc.
A/D Converter Interrupt, Configuring ....................... 235
Acquisition Requirements ........................................ 236
ADCON0 Register .................................................... 231
ADCON1 Register .................................................... 231
ADCON2 Register .................................................... 231
ADRESH Register ............................................ 231, 234
ADRESL Register .................................................... 231
Analog Port Pins, Configuring .................................. 238
Associated Registers ............................................... 240
Automatic Acquisition Time ...................................... 237
Calculating the Minimum Required
Configuring the Module ............................................ 235
Conversion Clock (T
Conversion Requirements ....................................... 386
Conversion Status (GO/DONE Bit) .......................... 234
Conversions ............................................................. 239
Converter Characteristics ........................................ 385
Operation in Power Managed Modes ...................... 238
Special Event Trigger (CCP) .................................... 240
Use of the CCP2 Trigger .......................................... 240
Load Conditions for Device
Parameter Symbology ............................................. 368
Temperature and Voltage Specifications ................. 369
Timing Conditions .................................................... 369
Mapping with Indexed Literal Offset Mode ................. 86
GO/DONE Bit ........................................................... 234
Asynchronous Receiver Transmitter (AUSART).
See AUSART.
MPASM Assembler .................................................. 345
Asynchronous Mode ................................................ 222
Acquisition Time .............................................. 236
Timing Specifications ....................................... 369
Associated Registers, Receive ........................ 225
Associated Registers, Transmit ....................... 223
Receiver ........................................................... 224
Setting up 9-Bit Mode with
Transmitter ....................................................... 222
Address Detect ........................................ 224
AD
) ........................................... 237
PIC18F6390/6490/8390/8490
Preliminary
Auto-Wake-up on Sync Break Character ......................... 210
B
Bank Select Register (BSR) .............................................. 71
Baud Rate Generator ...................................................... 183
BC .................................................................................... 303
BCF ................................................................................. 304
BF .................................................................................... 187
BF Status Flag ................................................................. 187
Block Diagrams
Baud Rate Generator (BRG) ................................... 220
Synchronous Master Mode ...................................... 226
Synchronous Slave Mode ........................................ 229
A/D ........................................................................... 234
Analog Input Model .................................................. 235
AUSART Receive .................................................... 224
AUSART Transmit ................................................... 222
Baud Rate Generator .............................................. 183
Capture Mode Operation ......................................... 150
Comparator
Comparator Analog Input Model .............................. 245
Comparator Output .................................................. 244
Comparator Voltage Reference ............................... 248
Compare Mode Operation ....................................... 151
Device Clock .............................................................. 36
EUSART Receive .................................................... 208
EUSART Transmit ................................................... 206
External Power-on Reset Circuit
Fail-Safe Clock Monitor ........................................... 290
Generic I/O Port Operation ...................................... 109
HLVD Module (with External Input) ......................... 252
Interrupt Logic ............................................................ 94
LCD Clock Generation ............................................. 262
LCD Driver Module .................................................. 257
LCD Resistor Ladder Connection ............................ 263
MSSP (I
MSSP (I
MSSP (SPI Mode) ................................................... 157
On-Chip Reset Circuit ................................................ 51
PLL (HS Mode) .......................................................... 33
PWM Operation (Simplified) .................................... 153
Reads from Flash Program Memory ......................... 88
Single Comparator ................................................... 243
Table Read Operation ............................................... 87
Timer0 in 16-Bit Mode ............................................. 132
Timer0 in 8-Bit Mode ............................................... 132
Timer1 ..................................................................... 136
Associated Registers ....................................... 220
Baud Rate Error, Calculating ........................... 220
Baud Rates, Asynchronous Modes ................. 221
High Baud Rate Select (BRGH Bit) ................. 220
Operation in Power Managed Modes .............. 220
Sampling ......................................................... 220
Associated Registers, Receive ........................ 228
Associated Registers, Transmit ....................... 227
Reception ........................................................ 228
Transmission ................................................... 226
Associated Registers, Receive ........................ 230
Associated Registers, Transmit ....................... 229
Reception ........................................................ 230
Transmission ................................................... 229
I/O Operating Modes (Diagram) ...................... 242
(Slow V
2
2
C Master Mode) ........................................ 181
C Mode) .................................................... 166
DD
Power-up) ........................................ 53
DS39629B-page 397