PIC18F8390-I/PT Microchip Technology, PIC18F8390-I/PT Datasheet - Page 407
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PIC18F8390-I/PT
Manufacturer Part Number
PIC18F8390-I/PT
Description
IC PIC MCU FLASH 4KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6310-IPT.pdf
(28 pages)
3.PIC18F6390-IPT.pdf
(414 pages)
4.PIC18F6390-IPT.pdf
(16 pages)
5.PIC18F6390-IPT.pdf
(12 pages)
6.PIC18F6390-IPT.pdf
(6 pages)
7.PIC18F6390-IPT.pdf
(4 pages)
8.PIC18F8490-IPT.pdf
(412 pages)
Specifications of PIC18F8390-I/PT
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
Number Of I /o
66
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8390-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8390-I/PT
Manufacturer:
MICRO
Quantity:
20 000
Timer1 .............................................................................. 135
Timer2 .............................................................................. 141
Timer3 .............................................................................. 143
Timing Diagrams
2004 Microchip Technology Inc.
16-Bit Read/Write Mode ........................................... 137
Associated Registers ............................................... 139
Interrupt .................................................................... 138
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt .................................................... 135
Resetting, Using a Special Event
TMR1H Register ...................................................... 135
TMR1L Register ....................................................... 135
Use as a Real-Time Clock ....................................... 138
Associated Registers ............................................... 142
Interrupt .................................................................... 142
Operation ................................................................. 141
Output ...................................................................... 142
PR2 Register ............................................................ 153
TMR2 to PR2 Match Interrupt .................................. 153
16-Bit Read/Write Mode ........................................... 145
Associated Registers ............................................... 145
Operation ................................................................. 144
Oscillator .......................................................... 143, 145
Overflow Interrupt ............................................ 143, 145
Special Event Trigger (CCP) .................................... 145
TMR3H Register ...................................................... 143
TMR3L Register ....................................................... 143
A/D Conversion ........................................................ 386
Acknowledge Sequence .......................................... 190
Asynchronous Reception ................................. 209, 225
Asynchronous Transmission ............................ 207, 223
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 205
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 210
Baud Rate Generator with Clock Arbitration ............ 184
BRG Overflow Sequence ......................................... 205
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 373
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision for Transmit and Acknowledge ........... 191
Capture/Compare/PWM (All CCP Modules) ............ 375
CLKO and I/O .......................................................... 372
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 69
Example SPI Master Mode (CKE = 0) ..................... 376
Example SPI Master Mode (CKE = 1) ..................... 377
Example SPI Slave Mode (CKE = 0) ....................... 378
Layout Considerations ..................................... 138
Trigger Output (CCP) ....................................... 138
(Back to Back) ......................................... 207, 223
Normal Operation ............................................ 210
During Start Condition ..................................... 193
Condition (Case 1) ........................................... 194
Condition (Case 2) ........................................... 194
Condition (SCL = 0) ......................................... 193
Condition (SDA Only) ...................................... 192
Condition (Case 1) ........................................... 195
Condition (Case 2) ........................................... 195
PIC18F6390/6490/8390/8490
Preliminary
Example SPI Slave Mode (CKE = 1) ....................... 379
External Clock (All Modes Except PLL) ................... 370
Fail-Safe Clock Monitor ........................................... 291
High/Low-Voltage Detect Characteristics ................ 367
High-Voltage Detect Operation (VDIRMAG = 1) ..... 254
I
I
I
I
I
I
I
I
I
I
I
I
I
LCD Interrupt Timing in Quarter-Duty
LCD Sleep Entry/Exit when SLPEN = 1
Low-Voltage Detect Operation
Master SSP I
Master SSP I
PWM Output ............................................................ 153
Repeat Start Condition ............................................ 186
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 211
Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 162
SPI Mode (Slave Mode, CKE = 0) ........................... 164
SPI Mode (Slave Mode, CKE = 1) ........................... 164
Synchronous Reception
Synchronous Transmission ............................. 212, 226
Synchronous Transmission
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 374
Transition for Entry to PRI_IDLE Mode ..................... 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 46
Transition for Wake from Sleep (HSPLL) .................. 45
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 44
Type-A in 1/2 Mux, 1/2 Bias Drive ........................... 266
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 380
C Bus Start/Stop Bits ............................................ 380
C Master Mode (7 or 10-Bit Transmission) ........... 188
C Master Mode (7-Bit Reception) ......................... 189
C Master Mode First Start Bit ................................ 185
C Slave Mode (10-Bit Reception, SEN = 0) .......... 174
C Slave Mode (10-Bit Reception, SEN = 1) .......... 179
C Slave Mode (10-Bit Transmission) .................... 175
C Slave Mode (7-Bit Reception, SEN = 0) ............ 172
C Slave Mode (7-Bit Reception, SEN = 1) ............ 178
C Slave Mode (7-Bit Transmission) ...................... 173
C Slave Mode General Call Address
C Stop Condition Receive or
Sequence (7 or 10-Bit Address Mode) ............ 180
Transmit Mode ................................................. 190
Cycle Drive ...................................................... 276
or CS1:CS0 = 00 ............................................. 277
(VDIRMAG = 0) ............................................... 253
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 373
V
(Master Mode, SREN) ............................. 214, 228
(Through TXEN) ...................................... 213, 227
(MCLR Tied to V
MCLR Not Tied to V
MCLR Not Tied to V
MCLR Tied to V
(INTOSC to HSPLL) ........................................ 289
PRI_RUN Mode ................................................. 44
PRI_RUN Mode (HSPLL) .................................. 43
DD
Rise > T
2
2
C Bus Data ....................................... 382
C Bus Start/Stop Bits ........................ 382
PWRT
DD
DD
) ............................................ 57
, V
) .......................................... 57
DD
DD
DD
, Case 1 ......................... 56
, Case 2 ......................... 56
Rise < T
DD
DS39629B-page 405
,
PWRT
............. 56