AT90CAN32-16AU Atmel, AT90CAN32-16AU Datasheet - Page 231
![IC MCU AVR 32K FLASH 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
AT90CAN32-16AU
Manufacturer Part Number
AT90CAN32-16AU
Description
IC MCU AVR 32K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN32-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT90CANx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
53
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
4
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN32-16AU
Manufacturer:
ATMEL
Quantity:
250
Part Number:
AT90CAN32-16AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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18.8.6
7679H–CAN–08/08
Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
Note that data is transmitted both from master to slave and vice versa. The master must instruct
the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multimaster sys-
tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the
master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 18-19. Combining Several TWI Modes to Access a Serial EEPROM
1. The transfer must be initiated
2. The EEPROM must be instructed what location should be read
3. The reading must be performed
4. The transfer must be finished
S
S = START
Transmitted from master to slave
SLA+W
A
Master Transmitter
ADDRESS
A
Rs = REPEATED START
Rs
Transmitted from slave to master
SLA+R
AT90CAN32/64/128
A
Master Receiver
DATA
P = STOP
A
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