AT90CAN32-16AU Atmel, AT90CAN32-16AU Datasheet - Page 252

• Manufacturer Part Number: AT90CAN32-16AU
• Description: IC MCU AVR 32K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN32-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• No. Of I/o's: 53
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.10 General CAN Registers
19.10.1
252
AT90CAN32/64/128
CAN General Control Register - CANGCON
• Bit 7 – ABRQ: Abort Request
This is not an auto resettable bit.
• Bit 6 – OVRQ: Overload Frame Request
This is not an auto resettable bit.
The overload frame can be traced observing OVFG in CANGSTA register (c.f.
page
• Bit 5 – TTC: Time Trigger Communication
• Bit 4 – SYNTTC: Synchronization of TTC
This bit is only used in TTC mode.
• Bit 3 – LISTEN: Listening Mode
• Bit 2 – TEST: Test Mode
Note:
• Bit 1 – ENA/STB: Enable / Standby Mode
Because this bit is a command and is not immediately effective, the ENFG bit in CANGSTA reg-
ister gives the true state of the chosen mode.
Initial Value
Read/Write
Bit
243).
– 0 - no request.
– 1 - abort request: a reset of CANEN1 and CANEN2 registers is done. The pending
– 0 - no request.
– 1 - overload frame request: send an overload frame after the next received frame.
– 0 - no TTC.
– 1 - TTC mode.
– 0 - the TTC timer is caught on SOF.
– 1 - the TTC timer is caught on the last bit of the EOF.
– 0 - no listening mode.
– 1 - listening mode.
– 0 - no test mode
– 1 - test mode: intend for factory testing and not for customer use.
communications are immediately disabled and the on-going one will be normally
terminated, setting the appropriate status flags.
Note that CANCDMOB register remain unchanged.
CAN may malfunction if this bit is set.
ABRQ
R/W
7
0
OVRQ
R/W
6
0
TTC
R/W
5
0
SYNTTC
R/W
0
4
LISTEN
R/W
3
0
TEST
R/W
2
0
ENA/STB
R/W
1
0
SWRES
R/W
0
0
CANGCON
Figure 19-9 on
7679H–CAN–08/08