ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 193

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

16.10.9
7647G–AVR–09/11
CAN Bit Timing Register 2 - CANBT2
• Bit 6:1 – BRP5:0: Baud Rate Prescaler
The period of the CAN controller system clock Tscl is programmable and determines the indi-
vidual bit timing.
If ‘BRP[5..0]=0’, see
Sample Point(s)” on page
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT1 is written.
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT2 is written.
• Bit 6:5 – SJW1:0: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the con-
troller must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period
may be shortened or lengthened by a re-synchronization.
• Bit 4 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT2 is written.
• Bit 3:1 – PRS2:0: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network.
It is twice the sum of the signal propagation time on the bus line, the input comparator delay
and the output driver delay.
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to
zero when CANBT2 is written.
Tscl
Tsjw
Tprs
Initial Value
Read/Write
=
=
=
Bit
-------------------------------------- -
clk
Tscl
Tscl
BRP[5:0]
IO
frequency
PRS[2:0]
SJW[1:0]
+
7
-
-
-
1
Section 16.4.3 “Baud Rate” on page 177
+
+
SJW1
1
R/W
1
6
0
194.
SJW0
R/W
5
0
Atmel ATmega16/32/64/M1/C1
4
-
-
-
PRS2
R/W
3
0
PRS1
R/W
2
0
and
PRS0
R/W
Section • “Bit 0 – SMP:
1
0
0
-
-
-
CANBT2
193