ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 313

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

25.9
25.9.1
7647G–AVR–09/11
Serial Downloading
Serial Programming Algorithm
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus
while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output). After RESET is set low, the Programming Enable instruction needs to be exe-
cuted first before program/erase operations can be executed. NOTE, in
304, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated
for the internal SPI interface.
Figure 25-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed program-
ming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega16/32/64/M1/C1, data is clocked on the rising edge of
SCK.
When reading data from the ATmega16/32/64/M1/C1, data is clocked on the falling edge of
SCK. See
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to
2. V
Figure 25-11
the XTAL1 pin.
CC
- 0.3V < AVCC < V
for timing details.
MOSI_A
MISO_A
SCK_A
ck
ck
CC
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
Atmel ATmega16/32/64/M1/C1
XTAL1
RESET
GND
(1)
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
(2)
ck
ck
>= 12MHz
>= 12MHz
Table 25-14 on page
313