ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 271
ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (7Mb)
21.2
21.3
7647G–AVR–09/11
Operation
Starting a Conversion
Figure 21-1. Digital to Analog Converter Block Schematic
The Digital to Analog Converter generates an analog signal proportional to the value of the
DAC registers value.
In order to have an accurate sampling frequency control, there is the possibility to update the
DAC input values through different trigger events.
The DAC is configured thanks to the DACON register. As soon as the DAEN bit in DACON
register is set, the DAC converts the value present on the DACH and DACL registers in accor-
dance with the register DACON setting.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering
is enabled by setting the DAC Auto Trigger Enable bit, DAATE in DACON. The trigger source
is selected by setting the DAC Trigger Select bits, DATS in DACON (See description of the
DATS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger
signal, the DAC converts the value present on the DACH and DACL registers in accordance
with the register DACON setting. This provides a method of starting conversions at fixed
intervals.
Detector
Edge
DAATE
DAC High bits
VRef
DACH
DATS2
10
DATS1
Atmel ATmega16/32/64/M1/C1
Update DAC
1
Trigger
DAC
10
0
DATS0
10
DACON
DACL
DAC Low bits
-
Result
DAC
DALA
Output
Driver
DAOE
DAEN
D2A pin
271
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