ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 217
ATMEGA64M1-15MZ
Manufacturer Part Number
ATMEGA64M1-15MZ
Description
MCU AVR 64KB FLASH 3PSC 32-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA64M1-15MZ.pdf
(367 pages)
Specifications of ATMEGA64M1-15MZ
Package / Case
32-VQFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Eeprom Size
2K x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
4K x 8
Program Memory Size
64KB (64K x 8)
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Connectivity
CAN, LIN, SPI, UART/USART
Core Size
8-Bit
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
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17.5.7.4
17.5.7.5
17.5.7.6
7647G–AVR–09/11
Data Length in Tx Response
Data Length after Error
Data Length in UART Mode
LRXDL (*)
LTXDL (*)
LIN bus
LBUSY
Figure 17-10. LIN1.3 - Tx Response - No error
Figure 17-11. Tx Response - Error
Note:
(*) : LRXDL & LTXDL updated by Rx Response or Tx Response task
• The user initializes LTXDL field before setting the Tx Response command,
• After setting the Tx Response command, LRXDL is reset by hardware,
• LTXDL will remain unchanged during Tx (during busy signal),
• LRXDL will count the number of transmitted bytes (during busy signal),
• If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the
• If no error occurs, LTXOK is set after the transmission of the CHECKSUM, LTXDL will be
• The UART mode forces LRXDL and LTXDL to 0 and disables the writing in LINDLR
• Note that after reset, LRXDL and LTXDL are also forced to 0.
number of transmitted bytes without error,
unchanged (and LRXDL = LTXDL).
register,
Information on response (ex: error on byte) is only available at the end of the serializa-
tion/de-serialization of the byte.
LIDOK
4
4
LIN bus
LBUSY
LRXDL
LTXDL
DATA-0
1
LCMD=Tx Response
st
Byte
4
4
0
DATA-0
1
LCMD=Tx Response
st
Byte
0
DATA-1
2
nd
Byte
1
Atmel ATmega16/32/64/M1/C1
DATA-1
2
nd
Byte
1
DATA-2
3
rd
Byte
2
LCMD2..0=000
ERROR
3
DATA-2
rd
Byte
DATA-3
2
4
th
Byte
b
3
LERR
LCMD2..0=000
CHECKSUM
4
b
LTXOK
217
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