ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 135
ATMEGA128A-MU
Manufacturer Part Number
ATMEGA128A-MU
Description
MCU 8BIT 128K ISP FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4KB
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ATMEGA128A-MU
Manufacturer:
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Quantity:
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Manufacturer:
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8151H–AVR–02/11
Table 15-2.
Table 15-3
PWM mode
Table 15-3.
Note:
Table 15-3
correct and frequency correct PWM mode.
COMnA1/COMnB1/
COMnA1/COMnB1/
COMnC1
COMnC1
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at BOTTOM.
0
0
1
1
0
0
1
1
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
Compare Output Mode, non-PWM
Compare Output Mode, Fast PWM
See “Fast PWM Mode” on page 126.
COMnA0/COMnB0/
COMnA0/COMnB0/
COMnC0
COMnC0
0
1
0
1
0
1
0
1
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
Toggle OCnA/OCnB/OCnC on compare match.
Clear OCnA/OCnB/OCnC on compare match
(set output to low level).
Set OCnA/OCnB/OCnC on compare match (set
output to high level).
Description
Normal port operation, OCnA/OCnB/OCnC
disconnected.
WGMn3:0 = 15: Toggle OCnA on Compare
Match, OCnB/OCnC disconnected (normal port
operation).
For all other WGMn settings, normal port
operation, OCnA/OCnB/OCnC disconnected.
Clear OCnA/OCnB/OCnC on compare match,
set OCnA/OCnB/OCnC at BOTTOM,
(non-inverting mode)
Set OCnA/OCnB/OCnC on compare match,
clear OCnA/OCnB/OCnC at BOTTOM,
(inverting mode)
for more details.
ATmega128A
135
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