ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 55

• Manufacturer Part Number: ATMEGA128A-MU
• Description: MCU 8BIT 128K ISP FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 4KB
• Ram Memory Size: 4KB
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4
10.5
8151H–AVR–02/11
Watchdog Timer
Timed Sequences for Changing the Configuration of the Watchdog Timer
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega128A resets and executes from the
Reset Vector. See
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, 3
different safety levels are selected by the Fuses M103C and WDTON as shown in Table 10-1.
Safety level 0 corresponds to the setting in ATmega103. There is no restriction on enabling the
WDT in any of the safety levels. Refer to
the Watchdog Timer” on page 55
Table 10-1.
Figure 10-7. Watchdog Timer
The sequence for changing configuration differs slightly between the three safety levels. Sepa-
rate procedures are described for each level.
M103C
Unprogrammed
Unprogrammed
Programmed
Programmed
Table 10-2 on page
WDT Configuration as a Function of the Fuse Settings of M103C and WDTON.
“Watchdog Reset” on page 54
WDTON
Unprogrammed
Programmed
Unprogrammed
Programmed
CC
= 5V. See characterization data for typical values at other V
OSCILLATOR
WATCHDOG
58. The WDR – Watchdog Reset – instruction resets the Watch-
for details.
Safety
Level
1
2
0
2
“Timed Sequences for Changing the Configuration of
WDT Initial
State
Disabled
Enabled
Disabled
Enabled
for timing details.
How to Disable
the WDT
Timed sequence
Always enabled
Timed sequence
Always enabled
ATmega128A
How to
Change
Time-out
Timed
sequence
Timed
sequence
No restriction
Timed
sequence
CC
levels. By
55