ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 202
ATMEGA128A-MU
Manufacturer Part Number
ATMEGA128A-MU
Description
MCU 8BIT 128K ISP FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4KB
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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21.2.2
21.3
21.3.1
21.3.2
8151H–AVR–02/11
Data Transfer and Frame Format
Electrical Interconnection
Transferring Bits
START and STOP Conditions
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical charac-
teristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below 100kHz,
and one valid for bus speeds up to 400kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 21-2. Data Validity
The master initiates and terminates a data transmission. The transmission is initiated when the
master issues a START condition on the bus, and it is terminated when the master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the master wishes to initiate a new transfer without relin-
quishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signalled by changing the level of the SDA
line when the SCL line is high.
Figure
21-1, both bus lines are connected to the positive supply voltage through
SDA
SCL
“Two-wire Serial Interface Characteristics” on page
Data Stable
Data Change
Data Stable
ATmega128A
325. Two
202
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