ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 37
ATMEGA128A-MU
Manufacturer Part Number
ATMEGA128A-MU
Description
MCU 8BIT 128K ISP FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4KB
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
ATMEGA128A-MU
Manufacturer:
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Manufacturer:
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8. System Clock and Clock Options
8.1
8.1.1
8.1.2
8151H–AVR–02/11
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
I/O
Figure 8-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 8-1.
The CPU clock is routed to parts of the system concerned with operation of the Atmel
core. Examples of such modules are the General Purpose Register File, the Status Register and
the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from per-
forming general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.’
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro-
nously when clk
CPU
Asynchronous
Timer/Counter
Timer/Counter
Oscillator
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
I/O
is halted, enabling TWI address reception in all sleep modes.
External RC
General I/O
Oscillator
modules
clk
clk
ASY
I/O
46. The clock systems are detailed below.
External clock
Control Unit
AVR Clock
Multiplexer
ADC
Clock
clk
Source clock
ADC
Reset Logic
CPU Core
clk
Oscillator
clk
Crystal
CPU
FLASH
Watchdog clock
Crystal Oscillator
Low-Frequency
RAM
Watchdog Timer
Watchdog
Oscillator
ATmega128A
“Power Manage-
Flash and
EEPROM
Calibrated RC
Oscillator
®
AVR
37
®
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