ATMEGA1280V-8AUR Atmel, ATMEGA1280V-8AUR Datasheet - Page 269
ATMEGA1280V-8AUR
Manufacturer Part Number
ATMEGA1280V-8AUR
Description
MCU AVR 128K FLASH 8MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1280V-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.9.5
23.9.6
2549M–AVR–09/10
TWAR – TWI (Slave) Address Register
TWAMR – TWI (Slave) Address Mask Register
• Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multimaster systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
• Bits 7:1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR.
detail.
Figure 23-22. TWI Address Match Logic, Block Diagram
Bit
(0xBA)
Read/Write
Initial Value
Bit
(0xBD)
Read/Write
Initial Value
TWAMR0
Address
TWAR0
Bit 0
TWA6
R/W
R/W
7
1
7
0
TWA5
R/W
R/W
6
1
6
0
Address Bit Comparator 6..1
ATmega640/1280/1281/2560/2561
TWA4
R/W
R/W
Address Bit Comparator 0
5
1
5
0
TWAM[6:0]
TWA3
R/W
R/W
4
1
4
0
Figure 23-22
TWA2
R/W
R/W
3
1
3
0
TWA1
R/W
R/W
shows the address match logic in
2
1
2
0
TWA0
R/W
R/W
1
1
1
0
TWGCE
R/W
Address
R
Match
0
0
0
–
0
TWAMR
TWAR
269
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