ATMEGA1280V-8AUR Atmel, ATMEGA1280V-8AUR Datasheet - Page 93

• Manufacturer Part Number: ATMEGA1280V-8AUR
• Description: MCU AVR 128K FLASH 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1280V-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2549M–AVR–09/10
• OC4B – Port H, Bit 4
OC4B, Output Compare Match B output: The PH4 pin can serve as an external output for the
Timer/Counter2 Output Compare B. The pin has to be configured as an output (DDH4 set) to
serve this function. The OC4B pin is also the output pin for the PWM mode timer function.
• OC4A – Port H, Bit 3
OC4C, Output Compare Match A output: The PH3 pin can serve as an external output for the
Timer/Counter4 Output Compare A. The pin has to be configured as an output (DDH3 set) to
serve this function. The OC4A pin is also the output pin for the PWM mode timer function.
• XCK2 – Port H, Bit 2
XCK2, USART2 External Clock: The Data Direction Register (DDH2) controls whether the clock
is output (DDH2 set) or input (DDH2 cleared). The XC2K pin is active only when the USART2
operates in synchronous mode.
• TXD2 – Port H, Bit 1
TXD2, USART2 Transmit Pin.
• RXD2 – Port H, Bit 0
RXD2, USART2 Receive pin: Receive Data (Data input pin for the USART2). When the
USART2 Receiver is enabled, this pin is configured as an input regardless of the value of DDH0.
When the USART2 forces this pin to be an input, a logical on in PORTH0 will turn on the internal
pull-up.
Table 12-25. Overriding Signals for Alternate Functions in PH7:PH4
Signal Name
DIEOE
DIEOV
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
AIO
DI
T4 INPUT
PH7/T4
0
0
0
0
0
0
–
0
0
–
ATmega640/1280/1281/2560/2561
OC2B ENABLE
PH6/OC2B
OC2B
0
0
0
0
–
0
0
0
–
OC4C ENABLE
PH5/OC4C
OC4C
0
0
0
0
–
0
0
0
–
OC4B ENABLE
PH4/OC4B
OC4B
0
0
0
0
–
0
0
0
–
93