PIC14000-20/SS Microchip Technology, PIC14000-20/SS Datasheet - Page 11

• Manufacturer Part Number: PIC14000-20/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-20/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.1
The clock input (from OSC1 or the internal oscillator) is
internally
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. The program counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow are shown in Figure 3-2.
FIGURE 3-2:
EXAMPLE 3-1:
1. MOVLW
2. MOVWF
3. CALL
4. BSF
1996 Microchip Technology Inc.
All instructions are single cycle, except for program branches. These take two cycles
since the fetched instruction is “flushed” from the pipeline while the new instruction is
being fetched and then executed.
Clocking Scheme/Instruction Cycle
(IN mode)
divided
CLKOUT
OSC1
Q4
CLOCK/INSTRUCTION CYCLE
PC
Q2
Q3
55h
PORTB
SUB_1
PORTA, BIT3
Q1
INSTRUCTION PIPELINE FLOW
by
Q1
four
Execute INST (PC-1)
Fetch INST (PC)
Q2
to
PC
Fetch 1
Q3
generate
Q4
four
Preliminary
Q1
Execute 1
Fetch 2
Execute INST (PC)
Fetch INST (PC+1)
Q2
PC+1
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 2
Fetch 3
Instruction Flow/Pipelining
Q4
Q1
Fetch SUB_1
Execute INST (PC+1)
Fetch INST (PC+2)
Execute 3
Q2
Fetch 4
PC+2
PIC14000
Q3
DS40122B-page 11
Q4
Fetch SUB_1
Flush
Flush
Internal
Phase
Clock