PIC14000-20/SS Microchip Technology, PIC14000-20/SS Datasheet - Page 50

• Manufacturer Part Number: PIC14000-20/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-20/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC14000
7.5.1.1
Once the I
for a START to occur. Following the START, the 8-bits
are shifted into the I
sampled with the rising edge of the clock (SCL) line.
The I
The address is compared on the falling edge of the
eighth clock (SCL) pulse. If the addresses match, and
the BF and I
happen:
• I
• Buffer Full (BF) bit is set
• ACK pulse is generated
• I
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 7-5). The five most
significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. The R/W bit (bit 0) must
specify a write, so the slave device will received the
second address byte. For a 10-bit address the first byte
would equal ‘1 1 1 1 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address are as follows, with steps 7-9 for
slave-transmitter:
1.
2.
3.
FIGURE 7-14: I
DS40122B-page 50
generated if enabled (I
ninth SCL pulse.
SDA
SCL
I
2
2
BF (I
2
I
2
CSR loaded into I
C Interrupt Flag (I
Receive first (high) byte of address (I
and UA are set).
Update I
address (clears UA and releases SCL line).
Read I
CIF (PIR1<3>)
COV (I
2
CSR<7:1> is compared to the I
2
CSTAT<0>)
S
2
2
CCON<6>)
2
ADDRESSING
C module has been enabled, the I
CBUF (clears BF) and clear I
2
A7 A6 A5 A4 A3 A2 A1
1
COV bits are clear, the following things
2
CADD with second (low) byte of
Receiving Address
2
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
3
2
2
CBUF
CIF) is set (interrupt is
2
4
CSR. All incoming bits are
2
CIE set) on falling edge of
5
6
R/W=0
7
8
2
CADD register.
ACK
9
2
CIF.
2
D7
1
CIF, BF
2
C waits
D6
2
Cleared in software
I
2
CBUF is read
Receiving Data
D5
Preliminary
3
D4
4
D3
5
D2
6
4.
5.
6.
7.
8.
9.
7.5.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the I
register is cleared. The received address is loaded into
the I
When the address byte overflow condition exists then
no acknowledge (ACK) pulse is given. An overflow
condition is defined as either the BF bit (I
is set or the I
(Figure 7-14).
An I
byte. The I
I
byte. In master mode with slave enabled, three inter-
rupt sources are possible. Reading BF, P and S will
indicate the source of the interrupt.
Caution: BF is set after receipt of eight bits and auto-
D1
2
7
CSTAT register is used to determine the status of the
D0
2
8
2
Receive second (low) byte of address (I
and UA are set).
Update I
(clears UA, if match releases SCL line).
Read I
Receive Repeated START.
Receive first (high) byte of address (I
BF are set).
Read I
CIF interrupt is generated for each data transfer
CBUF.
ACK
9
2
D7
1
2
2
RECEPTION
CIF bit must be cleared in software, and the
matically cleared after the I
However, the flag is not actually cleared
until receipt of the acknowledge pulse. Oth-
erwise extra reads appear to be valid.
CBUF (clears BF) and clear I
CBUF (clears BF) and clear I
2
D6
CADD with first (high) byte of address
2
still full. ACK is not sent.
D5
Receiving Data
3
because I
2
COV bit (I
D4
4
I
2
D3
5
COV is set
2
1996 Microchip Technology Inc.
CBUF is
D2
6
D1
7
2
D0
CCON<6>) is set
8
ACK
9
2
CBUF is read.
Bus Master
terminates
transfer
2
2
2
CIF
CIF.
CSTAT<0>)
2
P
2
CIF and
CIF, BF
2
CSTAT