PIC14000-20/SS Microchip Technology, PIC14000-20/SS Datasheet - Page 82

• Manufacturer Part Number: PIC14000-20/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-20/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC14000
10.6
The PIC14000 has several sources of interrupt:
• External interrupt from OSC1/PBTN pin
• I
• PORTC interrupt on change (pins RC<7:4> only)
• Timer0 overflow
• A/D timer overflow
• A/D converter capture event
• Programmable reference comparator interrupt
This section addresses the external and Timer0
interrupts only. Refer to the appropriate sections for
description of the serial port, programmable reference
and A/D interrupts.
INTCON records individual interrupt requests in flag
bits. It also has individual and global enable bits. The
peripheral interrupt flags reside in the PIR1 register.
Peripheral interrupt enable interrupts are contained in
the PIE1 register.
Global interrupt masking is controlled by GIE
(INTCON<7>). Individual interrupts can be disabled
through their corresponding mask bit in the INTCON
register. GIE is cleared on reset to mask interrupts.
When an interrupt is serviced, the GIE is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with
0004h, the interrupt vector. For external interrupt
events, such as the I
will be 3 or 4 instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for 1 or 2 cycle instructions. Once in the
interrupt service routine the source(s) of the interrupt
can be determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid infinite interrupt
requests. Individual interrupt flag bits are set
regardless of the status of their corresponding mask bit
or the GIE bit to allow polling.
FIGURE 10-9: INTERRUPT LOGIC SCHEMATIC
DS40122B-page 82
2
C port interrupt
PBIF
PBIE
RCIF
RCIE
Interrupts
ADCIF
ADCIE
CMIF
CMIE
2
C interrupt, the interrupt latency
OVFIF
OVFIE
I
I
2
2
CIF
CIE
Preliminary
PEIE
T0IF
T0IE
PEIF
The return from interrupt instruction, RETFIE, exits the
interrupt routine as well as sets the GIE bit to re-enable
interrupts.
1.
2.
3.
The method to ensure that interrupts are globally
disabled is:
1.
LOOP: BCF
Note 1: The individual interrupt flags will be set by
Note 2: If an interrupt occurs while the Global
An instruction clears the GIE bit while an
interrupt is acknowledged.
The program branches to the interrupt vector
and executes the Interrupt Service Routine.
The interrupt service routine completes with the
execution of the RETFIE instruction. This causes
the GIE bit to be set (enables interrupts), and the
program returns to the instruction after the one
which was meant to disable interrupts.
Ensure that the GIE bit was cleared by the
instruction, as shown in the following code:
BTFSC INTCON,GIE ; Global Interrupts Disabled?
GOTO
:
the specified condition even though the
corresponding
cleared (interrupt disabled) or the GIE bit is
cleared (all interrupts disabled).
Interrupt Enable (GIE) bit is being cleared,
the
re-enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
INTCON,GIE ; Disable Global Interrupts
LOOP
GIE
GIE
Wake-up (If in SLEEP mode)
or terminate long write
bit
; No, try again
; Yes, continue with program
;
1996 Microchip Technology Inc.
interrupt
may
flow
Interrupt to CPU
unintentionally
enable
bit
be
is