PIC14000-20/SS Microchip Technology, PIC14000-20/SS Datasheet - Page 58

• Manufacturer Part Number: PIC14000-20/SS
• Description: IC MCU OTP 4KX14 A/D 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 14r

Specifications of PIC14000-20/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 20
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: Slope A/D
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Processor Series: PIC14000
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 14 bit
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC14000
During conversion one or both of the following events
will occur:
1.
2.
In a capture event, the comparator trips when the slope
voltage on the CDAC output exceeds the input voltage,
causing the comparator output to transition from high to
low. This causes a transfer of the current timer count to
the capture register and sets the ADCIF flag
(PIR1<1>).
FIGURE 8-1:
DS40122B-page 58
Caution: Reading or writing the ADTMR register
Note:
(SLPCON<0>)
capture event
timer overflow
ADOFF
Bandgap Ref.
OSC1
Temp sensor
Oscillator
RESERVED
RESERVED
Prog. Ref. B
Prog. Ref. A
Internal
(nominal)
0.1 F
RD7/AN7
RD6/AN6
RD5/AN5
RD4/AN4
RA3/AN3
RA2/AN2
RA1/AN1
RA0/AN0
The correct sequence for writing the
ADTMR register is HI byte followed by LO
byte. Reversing this order will prevent the
A/D timer from running.
SREFLO
CDAC
SREFHI
during an A/D conversion cycle can pro-
duce unpredictable results and is not
recommended.
A/D BLOCK DIAGRAM
(Configuration Bit)
~2.5uA~5uA~10uA~20uA
FOSC
0
1
~100
ADCON0<7:4>
15
14
13
12
11
10
9
8
6
5
4
3
7
2
1
0
ADCON1<7:4>
4-Bit Current DAC
~ 1 kohm
(ADCON0<2>)
Analog
Mux
WRITE_TMR
4
Note 1
AMUXOE
ADRST (ADCON0<1>)
ADOFF
ADRST
Note 2
ADOFF
Preliminary
A/D
Capture Interrupt
(ADCIF, PIR1<1>)
Clock
Logic
Stop
A/D Capture
Note 1:
Note 2:
A CPU interrupt will be generated if bit ADCIE
(PIE1<1>) is set to ‘1’ (interrupt enabled). In addition,
the Global Interrupt Enable and Peripheral Interrupt
Enables (INTCON<7,6>) must also be set. Software is
responsible for clearing the ADCIF flag prior to the next
conversion cycle. Note that this interrupt can only occur
once per conversion cycle.
In a timer overflow condition, the timer rolls over from
FFFFh to 0000h, and a capture overflow flag (OVFIF)
is asserted (PIR1<0>). The timer continues to incre-
ment following a timer overflow. A CPU interrupt can be
generated if bit OVFIE (PIE1<0>) is set (interrupt
enabled). In addition, the Global Interrupt Enable and
Peripheral Interrupt Enables (INTCON<7,6>) must also
be set. Software is responsible for clearing the OVFIF
flag prior to the next conversion cycle.
ADTMRH
ADCAPH
RA0/AN0
Approximately 3.5 microsecond time constant
All current sources are disabled if ADRST = ‘1’
ADTMRL
ADCAPL
(OVFIF, PIR1<0>)
1996 Microchip Technology Inc.
Overflow
Timer
Internal
Data
Bus