DSPIC30F6012A-20E/PF Microchip Technology, DSPIC30F6012A-20E/PF Datasheet - Page 42

• Manufacturer Part Number: DSPIC30F6012A-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F6011A/6012A/6013A/6014A
4.2.3
Modulo Addressing can be applied to the Effective
Address calculation associated with any W register. It
is important to realize that the address boundaries
check for addresses less than, or greater than the
upper (for incrementing buffers), and lower (for decre-
menting buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
4.3
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.3.1
Bit-Reversed Addressing is enabled when:
1.
2.
3.
DS70143E-page 42
Note:
BWM (W register selection) in the MODCON
register is any value other than ‘15’ (the stack
cannot
Addressing) and
the BREN bit is set in the XBREV register and
the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
Bit-Reversed Addressing
MODULO ADDRESSING
APPLICABILITY
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (e.g.,
[W7+W2]) is used, modulo address cor-
rection is performed but the contents of
the register remain unchanged.
BIT-REVERSED ADDRESSING
IMPLEMENTATION
be
accessed
using
Bit-Reversed
If the length of a bit-reversed buffer is M = 2
then the last ‘N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’, which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other addressing mode or for
byte sized data, and normal addresses will be gener-
ated instead. When Bit-Reversed Addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the
LSb of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
Note:
Note:
All bit-reversed EA calculations assume
word sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo Addressing and Bit-Reversed
Addressing
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing will assume priority when active for the
X WAGU, and X WAGU Modulo Address-
ing will be disabled. However, Modulo
Addressing will continue to function in the X
RAGU.
© 2011 Microchip Technology Inc.
should
not
be
enabled
N
bytes,