DSPIC30F6012A-20E/PF Microchip Technology, DSPIC30F6012A-20E/PF Datasheet - Page 45

• Manufacturer Part Number: DSPIC30F6012A-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.0
The dsPIC30F Sensor and General Purpose Family has
up to 41 interrupt sources and 4 processor exceptions
(traps) which must be arbitrated based on a priority
scheme.
The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in the
interrupt vector to the Program Counter. The interrupt
vector is transferred from the program data bus into the
Program Counter via a 24-bit wide multiplexer on the
input of the Program Counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in
The interrupt controller is responsible for pre-processing
the interrupts and processor exceptions prior to them
being presented to the processor core. The peripheral
interrupts and traps are enabled, prioritized and con-
trolled using centralized Special Function Registers:
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
• IPC0<15:0>... IPC10<7:0>
• IPL<3:0>
• INTTREG<15:0>
© 2011 Microchip Technology Inc.
Note:
All interrupt request flags are maintained in these
three registers. The flags are set by their respective
peripherals or external signals, and they are
cleared via software.
All interrupt enable control bits are maintained in
these three registers. These control bits are used to
individually enable interrupts from the peripherals
or external signals.
The user assignable priority level associated with
each of these 41 interrupts is held centrally in these
twelve registers.
The current CPU priority level is explicitly stored in
the IPL bits. IPL<3> is present in the CORCON
register, whereas IPL<2:0> are present in the
STATUS register (SR) in the processor core.
The associated interrupt vector number and the
new CPU interrupt priority level are latched into
vector number (VECNUM<5:0>) and Interrupt level
(ILR<3:0>) bit fields in the INTTREG register. The
new interrupt priority level is the priority of the
pending interrupt.
INTERRUPTS
Table
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
(DS70157).
5-1.
dsPIC30F6011A/6012A/6013A/6014A
Reference
Manual”
• INTCON1<15:0>, INTCON2<15:0>
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers. Each
interrupt source is associated with an interrupt vector,
as shown in
highest and lowest maskable priorities, respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is pre-
vented even if the new interrupt is of higher priority than
the one currently being serviced.
Certain interrupts have specialized control bits for fea-
tures like edge or level triggered interrupts, interrupt-
on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the pro-
cessing of interrupts of priorities 6 and lower for a cer-
tain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program mem-
ory that corresponds to the interrupt. There are 63 dif-
ferent vectors within the IVT (refer to
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to
These locations contain 24-bit addresses and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execu-
tion of random data as a result of accidentally decre-
menting a PC into vector space, accidentally mapping
a data space address into vector space, or the PC roll-
ing over to 0x000000 after reaching the end of imple-
mented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.
Global interrupt control functions are derived from
these two registers. INTCON1 contains the con-
trol and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.
Note:
Note:
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
Assigning a priority level of ‘0’ to an inter-
rupt source is equivalent to disabling that
interrupt.
The IPL bits become read only whenever
the NSTDIS bit has been set to ‘1’.
Table
5-1. Levels 7 and 1 represent the
DS70143E-page 45
Table
5-1). These
Table
5-1).