PIC18C858-E/PT Microchip Technology, PIC18C858-E/PT Datasheet - Page 159
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C858-E/PT
Manufacturer Part Number
PIC18C858-E/PT
Description
IC MCU OTP 16KX16 CAN 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C858-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
68
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Data Rom Size
4 KB
Height
1 mm
Length
12 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
12 mm
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C858E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 159 of 366
- Download datasheet (7Mb)
15.4.10 ACKNOWLEDGE SEQUENCE TIMING
An acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2 register). When this bit is set, the SCL pin
is pulled low and the contents of the Acknowledge Data
bit (ACKDT) is presented on the SDA pin. If the user
wishes to generate an acknowledge, then the ACKDT
bit should be cleared. If not, the user should set the
ACKDT bit before starting an acknowledge sequence.
The baud rate generator then counts for one rollover
period (T
high). When the SCL pin is sampled high (clock arbitra-
tion), the baud rate generator counts for T
SCL pin is then pulled low. Following this, the ACKEN
bit is automatically cleared, the baud rate generator is
turned off and the MSSP module then goes into IDLE
mode (Figure 15-17).
15.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-17: ACKNOWLEDGE SEQUENCE WAVEFORM
2000 Microchip Technology Inc.
BRG
Note: T
) and the SCL pin is de-asserted (pulled
Sequence
SSPIF
Acknowledge sequence starts here,
SDA
SCL
BRG
= one baud rate generator period.
Set SSPIF at the end
of receive
ACKEN = 1, ACKDT = 0
Enable
Write to SSPCON2
bit
8
Advanced Information
D0
BRG
ACKEN
. The
Cleared in
software
T
BRG
ACK
15.4.11 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2 register). At the end of a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT register) is set.
A T
is set (Figure 15-18).
15.4.11.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
BRG
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
later, the PEN bit is cleared and the SSPIF bit
ACKEN automatically cleared
PIC18CXX8
Cleared in
software
DS30475A-page 159
BRG
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