PIC18C858-E/PT Microchip Technology, PIC18C858-E/PT Datasheet - Page 213
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C858-E/PT
Manufacturer Part Number
PIC18C858-E/PT
Description
IC MCU OTP 16KX16 CAN 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C858-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
68
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Data Rom Size
4 KB
Height
1 mm
Length
12 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
12 mm
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C858E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 213 of 366
- Download datasheet (7Mb)
17.5
17.5.1
The PIC18CXX8 includes two full receive buffers with
multiple acceptance filters for each. There is also a
separate Message Assembly Buffer (MAB), which acts
as a third receive buffer (see Figure 17-3).
17.5.2
Of the three receive buffers, the MAB is always commit-
ted to receiving the next message from the bus. The
remaining two receive buffers are called RXB0 and
RXB1 and can receive a complete message from the
protocol engine. The MCU can access one buffer while
the other buffer is available for message reception, or
holding a previously received message.
The MAB assembles all messages received. These
messages will be transferred to the RXB
if the acceptance filter criteria are met.
When a message is moved into either of the receive
buffers, the appropriate RXBnIF bit is set. This bit must
be cleared by the MCU when it has completed process-
ing the message in the buffer, in order to allow a new
message to be received into the buffer. This bit pro-
vides a positive lockout to ensure that the MCU has fin-
ished with the message before the PIC18CXX8
attempts to load a new message into the receive buffer.
If the RXBnIE bit is set, an interrupt will be generated to
indicate that a valid message has been received.
Note: The entire contents of the MAB is moved into
2000 Microchip Technology Inc.
Message Reception
RECEIVE MESSAGE BUFFERING
RECEIVE BUFFERS
the receive buffer once a message is
accepted. This means that regardless of the
type of identifier (standard or extended) and
the number of data bytes received, the entire
receive buffer is overwritten with the MAB
contents. Therefore, the contents of all regis-
ters in the buffer must be assumed to have
been modified when any message is
received.
N
buffers, only
Advanced Information
17.5.3
RXB0 is the higher priority buffer and has two message
acceptance filters associated with it. RXB1 is the lower
priority buffer and has four acceptance filters associ-
ated with it. The lower number of acceptance filters
makes the match on RXB0 more restrictive and implies
a higher priority for that buffer. Additionally, the
RXB0CON register can be configured such that if
RXB0 contains a valid message, and another valid
message is received, an overflow error will not occur
and the new message will be moved into RXB1,
regardless of the acceptance criteria of RXB1. There
are also two programmable acceptance filter masks
available, one for each receive buffer (see Section 4.5).
When a message is received, bits <3:0> of the RXB
register will indicate the acceptance filter number that
enabled reception, and whether the received message is a
remote transfer request.
The RXM bits set special receive modes. Normally,
these bits are set to 00 to enable reception of all valid
messages, as determined by the appropriate accep-
tance filters. In this case, the determination of whether
or not to receive standard or extended messages is
determined by the EXIDE bit in the acceptance filter
register. If the RXM bits are set to 01 or 10, the receiver
will accept only messages with standard or extended
identifiers, respectively. If an acceptance filter has the
EXIDE bit set such that it does not correspond with the
RXM mode, that acceptance filter is rendered useless.
These two modes of RXM bits can be used in systems
where it is known that only standard or extended mes-
sages will be on the bus. If the RXM bits are set to 11,
the buffer will receive all messages, regardless of the
values of the acceptance filters. Also, if a message has
an error before the end of frame, that portion of the
message assembled in the MAB before the error
frame, will be loaded into the buffer. This mode has
some value in debugging a CAN system and would not
be used in an actual system environment.
RECEIVE PRIORITY
PIC18CXX8
DS30475A-page 213
N
CON
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