PIC18C858-E/PT Microchip Technology, PIC18C858-E/PT Datasheet - Page 177
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18C858-E/PT
Manufacturer Part Number
PIC18C858-E/PT
Description
IC MCU OTP 16KX16 CAN 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C858-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
68
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Data Rom Size
4 KB
Height
1 mm
Length
12 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
12 mm
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C858E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 177 of 366
- Download datasheet (7Mb)
16.3
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA register).
In addition, enable bit SPEN (RCSTA register) is set, in
order to configure the RC6/TX/CK and RC7/RX/DT I/O
pins to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA register).
16.3.1
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one T
bit TXIF (PIR registers) is set. The interrupt can be
TABLE 16-8:
2000 Microchip Technology Inc.
Name
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
USART Synchronous Master Mode
USART SYNCHRONOUS MASTER
TRANSMISSION
USART Transmit Register
Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
CY
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
), the TXREG is empty and interrupt
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
Advanced Information
INT0IE
CREN
SYNC
TXIE
TXIP
Bit 4
TXIF
ADDEN
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
enabled/disabled by setting/clearing enable bit TXIE
(PIE registers). Flag bit TXIF will be set, regardless of
the state of enable bit TXIE, and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA register) shows the status of the TSR register.
TRMT is a read only bit, which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty. The TSR is not mapped in data memory,
so it is not available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Bit 1
TMR1IF
TMR1IE
TMR1IP
RX9D
TX9D
RBIF
Bit 0
PIC18CXX8
0000 000x
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
Value on
POR,
BOR
DS30475A-page 177
Value on all
0000 000u
0000 0000
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
RESETS
other
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