PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 145

• Manufacturer Part Number: PIC32MX795F512L-80I/PF
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/PF

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

24.0
The Ethernet Controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
Following are some of the key features of this module:
FIGURE 24-1:
 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
ETHERNET CONTROLLER
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” in the “PIC32MX Family
Reference Manual” , which is available
from
(www.microchip.com/PIC32).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Ethernet Controller
the
ETHERNET CONTROLLER BLOCK DIAGRAM
TX Bus
RX Bus
Master
Master
Registers
Control
DMA
Microchip
TX DMA
RX DMA
web
TX Flow Control
Checksum
RX Filter
Host IF
Ethernet DMA
site
Preliminary
TX BM
RX BM
PIC32MX5XX/6XX/7XX
• Supports 10/100 Mbps Data Transfer Rates
• Supports Full-Duplex and Half-Duplex Operation
• Supports RMII and MII PHY Interface
• Supports MIIM PHY Management Interface
• Supports both Manual and Automatic Flow Con-
• RAM Descriptor based DMA Operation for both
• Fully Configurable Interrupts
• Configurable Receive Packet Filtering
• Supports Packet Payload Checksum Calculation
• Supports Various Hardware Statistics Counters
Figure 24-1 shows a block diagram of the Ethernet
Controller.
trol
Receive and Transmit Path
- CRC Check
- 64-byte Pattern Match
- Broadcast, Multicast and Unicast packets
- Magic Packet™
- 64-bit Hash Table
- Runt Packet
TX Function
RX Function
RX Flow
Control
Configuration
MAC Control
Registers
and
MAC
MII/RMII
MIIM
IF
IF
DS61156B-page 145
External
PHY