PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 233

• Manufacturer Part Number: PIC32MX795F512L-80I/PF
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/PF

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

APPENDIX A:
This appendix provides an overview of considerations
for migrating from PIC32MX3XX/4XX devices to the
PIC32MX5XX/6XX/7XX family of devices. The code
developed for the PIC32MX3XX/4XX devices can be
ported to the PIC32MX5XX/6XX/7XX devices after
making the appropriate changes outlined below.
A.1
PIC32MX5XX/6XX/7XX devices do not support stop-
ping DMA transfers in Idle mode.
A.2
PIC32MX5XX/6XX/7XX devices have persistent inter-
rupts for some of the peripheral modules. This means
that the interrupt condition for these peripherals must
be cleared before the interrupt flag can be cleared.
For example, to clear a UART receive interrupt, the
user application must first read the UART Receive reg-
ister to clear the interrupt condition, and then clear the
associated UxIF flag to clear the pending UART inter-
rupt. In other words, the UxIF flag cannot be cleared by
software until the UART Receive register is read.
Table 32-1 outlines the peripherals and associated
interrupts
PIC32MX5XX/6XX/7XX
devices.
In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
and the transfer done interrupts were changed from 24
to 25.
TABLE A-1:
 2009 Microchip Technology Inc.
Input Capture
SPI
UART
ADC
PMP
Module
DMA
Interrupts
that
PIC32MX3XX/4XX VS. PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION
DIFFERENCES
are
To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF reg-
ister to obtain the number of data to receive/transmit below the level specified by the SRXI-
SEL<1:0> and STXISEL<1:0> bits.
TX interrupt will be generated as soon as the UART module is enabled.
Receive and Transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be read from or written to the UxRXREG or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.
MIGRATING FROM
PIC32MX3XX/4XX TO
PIC32MX5XX/6XX/7XX
DEVICES
implemented
versus
PIC32MX3XX/4XX
differently
Preliminary
on
Interrupt Implementation
PIC32MX5XX/6XX/7XX
DS61156B-page 233