PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 151

• Manufacturer Part Number: PIC32MX795F512L-80I/PF
• Description: IC MCU 32BIT 512KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/PF

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

27.0
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX. The PIC32MX devices offer a
total of nine methods and modes, organized into two
categories, that allow the user to balance power con-
sumption with device performance. In all of the meth-
ods and modes described in this section, power saving
is controlled by software.
27.1
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lower-
ing the PBCLK, and by individually disabling modules.
These methods are grouped into the following catego-
ries:
• FRC Run mode: the CPU is clocked from the FRC
• LPRC Run mode: the CPU is clocked from the
• S
In addition, the Peripheral Bus Scaling mode is avail-
able where peripherals are clocked at programmable
fraction of the CPU clock (SYSCLK).
27.2
The device supports two power-saving modes, Sleep
and Idle, both of which halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• P
• FRC Idle mode: the system clock is derived from
 2009 Microchip Technology Inc.
clock source with or without postscalers.
LPRC clock source.
S
the P
operate.
Peripherals continue to operate, but can
optionally be individually disabled.
the FRC with or without postscalers.
Peripherals continue to operate, but can option-
ally be individually disabled.
Note 1: This data sheet summarizes the features
OSC
OSC
OSC
OSC
Run mode: the CPU is clocked from the
clock source.
Idle mode: the system clock is derived from
2: Some registers and associated bits
POWER-SAVING FEATURES
Power Saving with CPU Running
CPU Halted Methods
. The system clock source continues to
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 10. “Power-Saving Fea-
tures”
Family Reference Manual” , which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
(DS61130) in the “PIC32MX
Preliminary
PIC32MX5XX/6XX/7XX
• S
• LPRC Idle mode: the system clock is derived from
• Sleep mode: the CPU, the system clock source,
27.3
Peripherals and the CPU can be halted or disabled to
further reduce power consumption.
27.3.1
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual periph-
eral module sections for descriptions of behavior in
Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted.
• The system clock source is typically shut down.
• There can be a wake-up delay based on the
• The Fail-Safe Clock Monitor (FSCM) does not
• The BOR circuit, if enabled, remains operative
• The WDT, if enabled, is not automatically cleared
• Some peripherals can continue to operate at lim-
• I/O pins continue to sink or source current in the
• The USB module can override the disabling of the
• Modules can be individually disabled by software
the S
Peripherals continue to operate, but can
optionally be individually disabled.
the LPRC.
Peripherals continue to operate, but can option-
ally be individually disabled. This is the lowest
power mode for the device with a clock running.
and any peripherals that operate from the system
clock source, are halted.
Some peripherals can operate in Sleep using spe-
cific clock sources. This is the lowest power mode
for the device.
See Section 27.3.3 “Peripheral Bus Scaling
Method” for specific information.
oscillator selection.
operate during Sleep mode.
during Sleep mode.
prior to entering Sleep mode.
ited functionality in Sleep mode. These peripher-
als include I/O pins that detect a change in the
input signal, WDT, ADC, UART, and peripherals
that use an external clock input or the internal
LPRC oscillator (e.g., RTCC, Timer1, and Input
Capture).
same manner as they do when the device is not in
Sleep.
Posc or FRC. Refer to the USB section for spe-
cific details.
prior to entering Sleep in order to further reduce
consumption.
OSC
OSC
Idle mode: the system clock is derived from
Power-Saving Operation
.
SLEEP MODE
DS61156B-page 151