ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 103

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.13 General data processing instructions
6500C–ATARM–8-Feb-11
Table 10-20
Table 10-20. Data processing instructions
Mnemonic
ADC
ADD
ADDW
AND
ASR
BIC
CLZ
CMN
CMP
EOR
LSL
LSR
MOV
MOVT
MOVW
MVN
ORN
ORR
RBIT
REV
REV16
REVSH
ROR
shows the data processing instructions:
Brief description
Add with Carry
Add
Add
Logical AND
Arithmetic Shift Right
Bit Clear
Count leading zeros
Compare Negative
Compare
Exclusive OR
Logical Shift Left
Logical Shift Right
Move
Move Top
Move 16-bit constant
Move NOT
Logical OR NOT
Logical OR
Reverse Bits
Reverse byte order in a word
Reverse byte order in each halfword
Reverse byte order in bottom halfword and
sign extend
Rotate Right
See
“ADD, ADC, SUB, SBC, and RSB” on
page 105
“ADD, ADC, SUB, SBC, and RSB” on
page 105
“ADD, ADC, SUB, SBC, and RSB” on
page 105
“AND, ORR, EOR, BIC, and ORN” on
page 108
“ASR, LSL, LSR, ROR, and RRX” on page
110
“AND, ORR, EOR, BIC, and ORN” on
page 108
“CLZ” on page 112
“CMP and CMN” on page 113
“CMP and CMN” on page 113
“AND, ORR, EOR, BIC, and ORN” on
page 108
“ASR, LSL, LSR, ROR, and RRX” on page
110
“ASR, LSL, LSR, ROR, and RRX” on page
110
“MOV and MVN” on page 114
“MOVT” on page 116
“MOV and MVN” on page 114
“MOV and MVN” on page 114
“AND, ORR, EOR, BIC, and ORN” on
page 108
“AND, ORR, EOR, BIC, and ORN” on
page 108
“REV, REV16, REVSH, and RBIT” on
page 117
“REV, REV16, REVSH, and RBIT” on
page 117
“REV, REV16, REVSH, and RBIT” on
page 117
“REV, REV16, REVSH, and RBIT” on
page 117
“ASR, LSL, LSR, ROR, and RRX” on page
110
SAM3S Preliminary
103