ATSAM3S4CA-CU Atmel, ATSAM3S4CA-CU Datasheet - Page 1083

• Manufacturer Part Number: ATSAM3S4CA-CU
• Description: IC MCU 32BIT 256KB FLASH 100BGA
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-CU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFBGA
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Package: 100LFBGA
• Device Core: ARM Cortex M3
• Family Name: AT91
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 79
• Interface Type: I2C/I2S/SPI/UART/USART/USB
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Number Of Timers: 6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

41.11.8
Table 30 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols refer to
41-31.
Table 41-52. Two-wire Serial Bus Requirements
Notes:
6500C–ATARM–8-Feb-11
Symbol
V
V
V
V
t
t
C
f
Rp
t
t
t
t
t
t
t
t
R
OF
TWCK
LOW
HIGH
HD;STA
SU;STA
HD;DAT
SU;DAT
SU;STO
HD;STA
IL
IH
HYS
OL
i
(1)
1. Required only for f
2. C
3.
4.
5. t
Two-wire Serial Interface Characteristics
The TWCK low Period is defined as follows:
The TWCK high period is defined as follows:
Parameter
Input Low-voltage
Input High-voltage
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
Rise Time for both TWD and TWCK
Output Fall Time from V
Capacitance for each I/O Pin
TWCK Clock Frequency
Value of Pull-up resistor
Low Period of the TWCK clock
High period of the TWCK clock
Hold Time (repeated) START Condition
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Hold Time (repeated) START Condition
CP_MCK
B
= capacitance of one bus line in pF. Per I2C Standard, C
= MCK Bus Period.
TWCK
> 100 kHz.
IHmin
to V
ILmax
T
T
low
high
=
10 pF < C
=
3 mA sink current
(
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
(
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
(
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
TWCK
CLDIV
Figure 41-31
(
CHDIV
Condition
> 100 kHz
> 100 kHz
> 100 kHz
> 100 kHz
> 100 kHz
> 100 kHz
> 100 kHz
> 100 kHz
> 100 kHz
≤ 100 kHz
≤ 100 kHz
≤ 100 kHz
≤ 100 kHz
≤ 100 kHz
≤ 100 kHz
≤ 100 kHz
≤ 100 kHz
≤ 100 kHz
b
b
Max = 400pF
×
< 400 pF
×
2
CKDIV
2
CKDIV
)
+
)
4 )
+
4 )
×
20 + 0.1C
20 + 0.1C
V
------------------------------------- -
×
V
------------------------------------- -
VDDIO
T
0.7xV
t
t
VDDIO
MCK
t
t
CP_MCK
CP_MCK
T
LOW -
LOW -
0.150
SAM3S Preliminary
MCK
3mA
t
t
t
t
t
t
t
t
Min
-0.3
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
3mA
(3)
(3)
(4)
(4)
–
0
0
0
-
VDDIO
–
3 x
3 x
–
b
b
0,4V
(5)
(5)
(1)(2)
(1)(2)
0,4V
3 x T
3 x T
0.3 V
V
1000ns
------------------ -
CC
300ns
--------------- -
Max
300
250
400
CP_MCK
CP_MCK
0.4
10
C
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ 0.3
VDDIO
b
b
(5)
(5)
Units
kHz
ns
ns
pF
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
Figure
V
V
V
V
Ω
Ω
1083