P89LPC9408FBD,557 NXP Semiconductors, P89LPC9408FBD,557 Datasheet - Page 38

• Manufacturer Part Number: P89LPC9408FBD,557
• Description: IC 80C51 MCU FLASH 8K 64-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9408FBD,557

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 64-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LED, POR, PWM, WDT
• Number Of I /o: 23
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10097 - KIT FOR LCD DEMO LPC9408EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3228; 935280583557; P89LPC9408FBD

Philips Semiconductors
P89LPC9408_1
Product data sheet
Fig 15. SPI block diagram
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
7.22 SPI
The P89LPC9408 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in
Master mode or up to 3 Mbit/s in Slave mode. It has a transfer completion flag and write
collision flag protection.
The SPI interface has three pins: SPICLK, MOSI, and MISO:
Typical connections are shown in
•
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
interrupt
request
SPI clock (master)
SPI
MSTR
SPEN
8-bit two-clock 80C51 core with 32 segment
Rev. 01 — 16 December 2005
internal
data
bus
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
Figure 16
clock
through
Figure
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
18.
P89LPC9408
4 LCD driver, 10-bit ADC
M
M
M
S
S
S
CONTROL
LOGIC
PIN
002aab466
MISO
P2.3
MOSI
P2.2
SPICLK
P2.5
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