LPC2368FET100,518 NXP Semiconductors, LPC2368FET100,518 Datasheet - Page 46

• Manufacturer Part Number: LPC2368FET100,518
• Description: IC ARM7 MCU FLASH 512K 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2300r

Specifications of LPC2368FET100,518

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 58K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC23
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 58 KB
• Interface Type: CAN/I2C/I2S/SPI/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA100, MCB2360, MCB2360U, MCB2360UME
• Development Tools By Supplier: OM10095, OM11042
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 100TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4917 - DEVELOPMENT BOARD FOR LPC2368622-1022 - BOARD SCKT ADAPTER FOR TFBGA100MCB2360UME - BOARD EVAL MCB2360 + ULINK-MEMCB2360U - BOARD EVAL MCB2360 + ULINK2622-1019 - BOARD FOR LPC2106 48-LQFP568-4014 - BOARD EVAL FOR LPC236X ARM568-3999 - BOARD EVAL FOR LPC23 ARM MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935285102518; LPC2368FET100-T; LPC2368FET100-T

NXP Semiconductors
LPC2364_65_66_67_68_6
Product data sheet
Fig 11. External clock timing (with an amplitude of at least V
Fig 12. Differential data-to-EOP transition skew and EOP width
Fig 13. MISO line set-up time in SSP Master mode
T
PERIOD
differential
data lines
10.1 Timing
MOSI
MISO
shifting edges
SCK
n × T
differential data to
crossover point
SE0/EOP skew
PERIOD
+ t
FDEOP
t
CHCL
Rev. 06 — 1 February 2010
t
su(SPI_MISO)
t
CLCX
crossover point
i(RMS)
T
extended
cy(clk)
= 200 mV)
t
CLCH
LPC2364/65/66/67/68
t
Single-chip 16-bit/32-bit microcontrollers
CHCX
sampling edges
002aaa907
source EOP width: t
receiver EOP width: t
002aad326
© NXP B.V. 2010. All rights reserved.
FEOPT
002aab561
EOPR1
, t
EOPR2
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