LPC2468FET208,551 NXP Semiconductors, LPC2468FET208,551 Datasheet - Page 59

• Manufacturer Part Number: LPC2468FET208,551
• Description: IC ARM7 MCU FLASH 512K 208TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2468FET208,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 208-TFBGA
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN/I2S/ISP/SSP/UART/USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 6
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, IRD-LPC2468-DEV, SAB-TFBGA208, KSK-LPC2468-PL
• Development Tools By Supplier: OM10100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 208TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1025 - KIT DEV IND REF DESIGN LPC2468622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4358 - DISPLAY QVGA TFT FOR OM10100568-4309 - BOARD EXTENSION LPCSTICK568-4308 - EVAL LPC-STICK WITH LPC2468MCB2400U - BOARD EVAL MCB2400 + ULINK2MCB2400 - BOARD EVAL FOR NXP LPC246X SER622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4262; 935283234551; LPC2468FET208-S

Table 14.
C
Symbol
Common to read and write cycles
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
CSLAV
OELAV
CSLOEL
am
h(D)
CSHOEH
OEHANV
OELOEH
BLSLAV
CSHBLSH
CSLWEL
CSLBLSL
WELDV
CSLDV
WELWEH
BLSLBLSH
WEHANV
L
= 30 pF, T
Parameter
CS LOW to address valid
time
OE LOW to address valid
time
CS LOW to OE LOW time
memory access time
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
BLS LOW to address valid
time
CS HIGH to BLS HIGH time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH
time
WE HIGH to address invalid
time
Dynamic characteristics: Static external memory interface
amb
11.5 Static external memory interface
=
−
40
°
C to 85
[1][2]
[1][6]
°
C, V
[1]
DD(DCDC)(3V3)
Conditions
= V
DD(3V3)
[3][4]
[5]
[3]
[3]
[3]
= 3.0 V to 3.6 V, AHB clock = 1 MHz
Min
−0.29
−0.29
−0.78 + T
(WAITRD − WAITOEN + 1) ×
T
0
−0.49
−0.20
−0.59 + (WAITRD −
WAITOEN + 1) × T
−0.39
−0.88
−0.88 + T
WAITWEN)
−0.88
0.68
0
−0.78 + T
(WAITWR − WAITWEN + 1)
−0.88 + T
(WAITWR − WAITWEN + 3)
0 + T
cy(CCLK)
cy(CCLK)
− 8.11
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
× WAITOEN 0 + T
× (1 +
×
×
cy(CCLK)
Typ
0.20
0.20
(WAITRD − WAITOEN + 1) ×
T
-
0
0.20
0 + (WAITRD − WAITOEN +
1) × T
0
0.49
0.10 + T
WAITWEN)
0.49
2.54
2.64
0 + T
WAITWEN + 1)
0 + T
WAITWEN + 3)
0.20 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 9.57
× WAITOEN
× (WAITWR −
× (WAITWR −
× (1 +
2.54
2.54
0.49 + T
2.44
2.54
0.68
0.98
Max
(WAITRD − WAITOEN + 1) ×
T
-
0.20
0.10 + (WAITRD −
WAITOEN + 1) × T
0.20 + T
WAITWEN)
5.86
4.79
0.10 + T
(WAITWR − WAITWEN + 1)
0.59 + T
(WAITWR − WAITWEN + 3)
2.74 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 12.70
× WAITOEN
× (1 +
×
×
cy(CCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns