LH7A400N0G000B5;55 NXP Semiconductors, LH7A400N0G000B5;55 Datasheet - Page 34

IC ARM9 BLUESTREAK MCU 256BGA

LH7A400N0G000B5;55

Manufacturer Part Number
LH7A400N0G000B5;55
Description
IC ARM9 BLUESTREAK MCU 256BGA
Manufacturer
NXP Semiconductors
Series
BlueStreak ; LH7Ar
Datasheet

Specifications of LH7A400N0G000B5;55

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, IrDA, Microwire, MMC, SmartCard, SPI, SSI, SSP, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
60
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.71 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Controller Family/series
(ARM9)
No. Of I/o's
60
Ram Memory Size
80KB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Processor Series
LH7A4
Core
ARM9TDMI
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
568-4334
935285038557
LH7A400
34
A[27:0]
D[31:0]
nCS[7:0]
SA[13:0]
SA[17:16]/SB[1:0]
D[31:0]
nCAS
nRAS
nSWE
SCKE[1:0]
DQM[3:0]
nSCS[3:0]
nPCREG
D[31:0]
nPCCE1
nPCCE2
nPCOE
nPCWE
PCDIR
SIGNAL
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE
Input
Input
Input
ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states × HCLK period])
LOAD
50 pF
50 pF
50 pF
30 pF
50 pF
50 pF
50 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
50 pF
30 pF
30 pF
30 pF
30 pF
30 pF
PCMCIA INTERFACE SIGNALS (+ wait states × HCLK period)
tOVDREG
tOHDREG
SYMBOL
tOHSDW
tOVSDW
tOVPCD
tOHPCD
tOVCE1
tOHCE1
tOVCE2
tOHCE2
tOHWE
tDVWE
tDHWE
tOVDQ
tOHOE
tOVWE
tDHBE
tDSCS
tDHCS
tDSOE
tDHOE
tDHBE
tAHCS
tOVCA
tOHCA
tOVRA
tOHRA
tOVSC
tOHSC
tOVOE
tDVBE
tDSBE
tAVCS
tOHA
tOHD
tOVD
tOVC
tOVD
tOHD
SYNCHRONOUS MEMORY INTERFACE SIGNALS
tOVA
tOVB
tIHD
tIHD
tWC
tWS
tISD
tISD
tRC
tCS
Table 12. AC Signal Characteristics
Rev. 01 — 16 July 2007
4 × tHCLK – 7.0 ns
4 × tHCLK – 7.0 ns
2 × tHCLK – 3.0 ns
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
4 × tHCLK – 5 ns
3 × tHCLK – 5 ns
3 × tHCLK – 5 ns
4 × tHCLK – 5 ns
NXP Semiconductors
tHCLK – 6.0 ns
tHCLK – 7.0 ns
tHCLK – 5.0 ns
tHCLK – 7.0 ns
tHCLK – 4.0 ns
1.5
1.5
1.0
1.5
1.5
1.5
1.5
tHCLK ns
tHCLK
3
1.5ns
3
3
15 ns
15 ns
15 ns
MIN.
0 ns
0 ns
0 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
2 ns
/1.5
/2.5
/1.5
3
3
3
3
/2
/2
/2
/2
4
4
4
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
4 × tHCLK + 7.5 ns
4 × tHCLK + 7.5 ns
2 × tHCLK + 3.0 ns
tHCLK – 2.0 ns
tHCLK + 2.0 ns
tHCLK – 1.0 ns
tHCLK + 3.0 ns
tHCLK + 4.5 ns
tHCLK - 10 ns
tHCLK + 1 ns
tHCLK + 1 ns
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
tHCLK ns
tHCLK
tHCLK
tHCLK
tHCLK
tHCLK
tHCLK
MAX.
3
3
3
3
3
3
3
3
3
/7.5
/7.5
/7.5
/7.5
/7.5
/7.5
/7.5
/7.5
/7.5
4
4
4
4
4
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Write Cycle Time
Wait State Width
Data Valid to Write Edge (nWE invalid)
Data Hold after Write Edge (nWE invalid)
Data Valid to nBLE Invalid
Data Hold after nBLE Invalid
Data Setup to nCSx Invalid
Data Hold to nCSx Invalid
Data Setup to nOE Invalid
Data Hold to nOE Invalid
Data Setup to nBLE Invalid
Data Hold to nBLE Invalid
nCSx Width
Address Valid to nCSx Valid
Address Hold after nCSx Invalid
Address Valid
Address Hold
Bank Select Valid
Data Hold
Data Valid
Data Setup
Data Hold
CAS Valid
CAS Hold
RAS Valid
RAS Hold
Write Enable Valid
Write Enable Hold
Clock Enable Valid
Data Mask Valid
Synchronous Chip Select Valid
Synchronous Chip Select Hold
nREG Valid
nREG Hold
Data Valid
Data Hold
Data Setup Time
Data Hold Time
Chip Enable 1 Valid
Chip Enable 1 Hold
Chip Enable 2 Valid
Chip Enable 2 Hold
Output Enable Valid
Output Enable Hold
Write Enable Valid
Write Enable Hold
Card Direction Valid
Card Direction Hold
32-Bit System-on-Chip
Preliminary data sheet
DESCRIPTION
1

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