ST72F63BK2U1TR STMicroelectronics, ST72F63BK2U1TR Datasheet - Page 107

• Manufacturer Part Number: ST72F63BK2U1TR
• Description: IC MCU 8BIT 8K FLASH 40-QFN
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F63BK2U1TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-QFN
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SCI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7MDTU3-EPB/US, ST72F63B-SK/RAIS, ST7MDTU3-EMU3, STX-RLINK
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8 bit, 8 Channel / 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST7263Bxx
Note:
Table 36.
Address
(Hex.)
25
26
Register
DMAR
Name
Reset
Reset
Once transmission and/or reception are enabled, registers EPnRA and/or EPnRB
(respectively) must not be modified by software, as the hardware can change their value on
the fly.
When the operation is completed, they can be accessed again to enable a new operation.
Interrupt handling
Start of Frame (SOF)
The interrupt service routine may monitor the SOF events for a 1 ms synchronization event
to the USB bus. This interrupt is generated at the end of a resume sequence and can also
be used to detect this event.
USB Reset (RESET)
When this event occurs, the DADDR register is reset, and communication is disabled in all
endpoint registers (the USB interface will not respond to any packet). Software is
responsible for reenabling endpoint 0 within 10 ms of the end of reset. To do this, set the
STAT_RX bits in the EP0RB register to VALID.
Suspend (SUSP)
The CPU is warned about the lack of bus activity for more than 3 ms, which is a suspend
request. The software should set the USB interface to suspend mode and execute an ST7
HALT instruction to meet the USB-specified power constraints.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which causes an ESUSP interrupt. The ST7
automatically terminates Halt mode.
Correct Transfer (CTR)
1.
2.
3.
USB register map and reset values
PIDR
value
value
When this event occurs, the hardware automatically sets the STAT_TX or STAT_RX to
NAK. Every valid endpoint is NAKed until software clears the CTR bit in the ISTR
register, independently of the endpoint number addressed by the transfer which
generated the CTR interrupt. If the event triggering the CTR interrupt is a SETUP
transaction, both STAT_TX and STAT_RX are set to NAK.
Read the PIDR to obtain the token and the IDR to get the endpoint number related to
the last transfer. When a CTR interrupt occurs, the TP3-TP2 bits in the PIDR register
and EP1-EP0 bits in the IDR register stay unchanged until the CTR bit in the ISTR
register is cleared.
Clear the CTR bit in the ISTR register.
DA15
TP3
7
x
x
DA14
TP2
6
x
x
Doc ID 7516 Rev 8
DA13
5
0
0
x
DA12
4
0
0
x
DA11
3
0
0
x
RX_SEZ
DA10
2
0
x
On-chip peripherals
RXD
DA9
1
0
x
107/186
DA8
0
0
0
x