Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 169
![IC Z8 ENCORE MCU FLASH 8K 28SSOP](/photos/12/33/123304/z8f0813hj005eg_sml.jpg)
Z8F0813HJ005EG
Manufacturer Part Number
Z8F0813HJ005EG
Description
IC Z8 ENCORE MCU FLASH 8K 28SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0813PH005SC.pdf
(227 pages)
Specifications of Z8F0813HJ005EG
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-4182
Z8F0813HJ005EG
Z8F0813HJ005EG
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Oscillator Control Register Definitions
PS025203-0405
Caution:
Oscillator Control Register
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate, allowing execution of a clock failure vector and software rou-
tines that either remedy the oscillator failure or issue a failure alert. This automatic switch-
over is not available if the Watch-Dog Timer is the primary oscillator. It is also unavailable
if the Watch-Dog Timer oscillator is disabled, though it is not necessary to enable the
Watch-Dog Timer reset function outlined in the Watch-Dog Timer chapter of this docu-
ment on page 81.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1KHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but non-failing clock can generate a failure condition. Under
these conditions, do not enable the clock failure circuitry (POFEN must be deasserted in
the OSCCTL register).
Watch-Dog Timer Failure
In the event of a Watch-Dog Timer oscillator failure, a similar non-maskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watch-Dog Timer failure, it is no longer possible to detect a
primary oscillator failure. The failure detection circuitry does not function if the Watch-
Dog Timer is used as the primary oscillator or if the Watch-Dog Timer oscillator has been
disabled. For either of these cases, it is necessary to disable the detection circuitry by deas-
serting the WDFEN bit of the OSCCTL register.
The Watch-Dog Timer oscillator failure detection circuit counts system clocks while look-
ing for a Watch-Dog Timer clock. The logic counts 8004 system clock cycles before deter-
mining that a failure has occurred. The system clock rate determines the speed at which
the Watch-Dog Timer failure can be detected. A very slow system clock results in very
slow detection times.
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry and selects the primary oscillator,
which becomes the system clock.
The Oscillator Control Register must be unlocked before writing. Writing the two step
sequence
is locked at successful completion of a register write to the OSCCTL.
It is possible to disable the clock failure detection circuitry as well as all functioning
clock sources. In this case, the Z8 Encore!
and can only be recovered by Power-On-Reset.
E7H
followed by
18H
P R E L I M I N A R Y
to the Oscillator Control Register unlocks it. The register
®
Z8F0823 Series device ceases functioning
Z8 Encore!
Product Specification
®
Z8F0823 Series
Oscillator Control
152
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