Z8F0813HJ005EG Zilog, Z8F0813HJ005EG Datasheet - Page 60
![IC Z8 ENCORE MCU FLASH 8K 28SSOP](/photos/12/33/123304/z8f0813hj005eg_sml.jpg)
Z8F0813HJ005EG
Manufacturer Part Number
Z8F0813HJ005EG
Description
IC Z8 ENCORE MCU FLASH 8K 28SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0813PH005SC.pdf
(227 pages)
Specifications of Z8F0813HJ005EG
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-4182
Z8F0813HJ005EG
Z8F0813HJ005EG
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BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025203-0405
Table 24. Port A–C STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)
PSMRE7
PHDE7
R/W
R/W
If 04H in Port A–C Address Register, accessible through the Port A–C Control Register
If 05H in Port A–C Address Register, accessible through the Port A–C Control Register
0
0
7
7
Port A–C High Drive Enable Sub-Registers
The Port A–C High Drive Enable sub-register (Table 23) is accessed through the Port
A–C Control register by writing
the Port A–C High Drive Enable sub-registers to 1 configures the specified port pins for
high current output drive operation. The Port A–C High Drive Enable sub-register affects
the pins directly and, as a result, alternate functions are also affected.
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–C STOP Mode Recovery Source Enable Sub-Registers
The Port A–C STOP Mode Recovery Source Enable sub-register (Table 24) is accessed
through the Port A–C Control register by writing
Setting the bits in the Port A–C STOP Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates
STOP Mode Recovery.
PSMRE[7:0]—Port STOP Mode Recovery Source Enabled
0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this
pin during STOP mode do not initiate STOP Mode Recovery.
1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on
this pin during STOP mode initiates STOP Mode Recovery.
Table 23. Port A–C High Drive Enable Sub-Registers (PxHDE)
PSMRE6
PHDE6
R/W
R/W
6
0
6
0
PSMRE5
PHDE5
R/W
R/W
5
0
5
0
P R E L I M I N A R Y
PSMRE4
PHDE4
04H
R/W
R/W
0
0
4
4
to the Port A–C Address register. Setting the bits in
PSMRE3
PHDE3
R/W
R/W
3
0
3
0
05H
to the Port A–C Address register.
PSMRE2
PHDE2
Z8 Encore!
R/W
R/W
0
0
2
2
Product Specification
PSMRE1
PHDE1
®
R/W
R/W
General-Purpose I/O
1
0
1
0
Z8F0823 Series
PSMRE0
PHDE0
R/W
R/W
0
0
0
0
43
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