ST7FLITE29F1B6 STMicroelectronics, ST7FLITE29F1B6 Datasheet - Page 72
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ST7FLITE29F1B6
Manufacturer Part Number
ST7FLITE29F1B6
Description
IC MCU 8BIT 8K FLASH 20-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST7FLITE29F1B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ST7FLITE2x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ST7LITE2
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
SS internal must be held high continuously.
Figure 44. Generic SS Timing Diagram
Figure 45. Hardware/Software Slave Select Management
72/133
1
MOSI/MISO
(if CPHA=0)
(if CPHA=1)
Figure
Master SS
Slave SS
Slave SS
45)
SS external pin
SSI bit
Byte 1
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA=1 (data latched on 2nd clock edge):
If CPHA=0 (data latched on 1st clock edge):
SS internal
Byte 2
– SS internal must be held low during the entire
– SS internal must be held low during byte
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
11.4.5.3).
44):
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