ST7FLITE29F1B6 STMicroelectronics, ST7FLITE29F1B6 Datasheet - Page 94
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ST7FLITE29F1B6
Manufacturer Part Number
ST7FLITE29F1B6
Description
IC MCU 8BIT 8K FLASH 20-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST7FLITE29F1B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ST7FLITE2x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ST7LITE2
13.3.2 Operating conditions with Low Voltage Detector (LVD)
T
Notes:
1. Not tested in production.
2. Not tested in production. The V
When the V
3. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is
recommended to pull V
page 112
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T
Note:
1. Not tested in production.
13.3.4 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
94/133
1
V
V
V
Vt
t
I
V
V
V
∆V
V
V
V
t
A
A
g(VDD)
DD(LVD
STARTUP
Symbol
Symbol
Symbol
IT+
IT-
hys
IT+
IT-
hys
DD(RC)
DD(x4PLL)
DD(x8PLL)
POR
= -40 to 85°C, unless otherwise specified
= -40 to 85°C, unless otherwise specified
IT-
(LVD)
(AVD)
(LVD)
(AVD)
)
and note 4.
DD
Reset release threshold
(V
Reset generation threshold
(V
LVD voltage threshold hysteresis
V
Filtered glitch delay on V
LVD/AVD current consumption
1=>0 AVDF flag toggle threshold
(V
0=>1 AVDF flag toggle threshold
(V
AVD voltage threshold hysteresis
Voltage drop between AVD flag set
and LVD reset activation
Internal RC Oscillator operating voltage
x4 PLL operating voltage
x8 PLL operating voltage
PLL Startup time
DD
slope is outside these values, the LVD may not ensure a proper reset of the MCU.
DD
DD
DD
DD
rise time rate
rise)
fall)
rise)
fall)
DD
Parameter
Parameter
down to 0V to ensure optimum restart conditions. Refer to circuit example in
Parameter
2)3)
DD
rise time rate condition is needed to insure a correct device power-on and LVD reset.
DD
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
V
Not detected by the LVD
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
V
V
IT+
IT+
DD
(LVD)
(AVD)
fall
Conditions
Conditions
-V
-V
IT-
IT-
Conditions
(LVD)
(AVD)
3.40
2.65
4.00
4.40
3.90
3.20
3.80
3.20
2.40
4.30
3.70
2.90
Min
Min
20
Min
2.4
2.4
3.3
1)
1)
1)
1)
1)
1)
Typ
Typ
4.25
3.60
2.90
4.05
3.40
2.70
4.70
4.10
3.40
4.60
3.90
3.20
0.45
200
220
150
Typ
60
4.30
3.65
20000
2.90
4.90
4.10
3.40
Max
Max
4.50
3.80
3.15
5.00
4.30
3.60
150
Max
5.5
3.3
5.5
Figure 84 on
1)
1)
1)
1)
1)
1)
cycles
µs/V
Unit
Unit
(f
clock
input
mV
mV
Unit
PLL
µA
ns
V
V
V
PLL
V
)