ST72F324J6T6 STMicroelectronics, ST72F324J6T6 Datasheet - Page 105
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ST72F324J6T6
Manufacturer Part Number
ST72F324J6T6
Description
IC MCU 8BIT 32K 44-TQFP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST72F324J6T6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
ST7
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
No. Of Pwm Channels
1
Rohs Compliant
Yes
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
3.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7F521-IND/USB, ST7232X-EVAL, ST7MDT20-DVP3, ST7MDT20J-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Cpu Family
ST7
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
1KB
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3.8V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
For Use With
497-8222 - UPS (LINE INTERACTIVE - 450W)497-8436 - BOARD EVAL UPS 450W VOUT=220V497-6421 - BOARD EVAL DGTL BATT CHGR DESIGN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
In Transition
Other names
497-2108
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST72F324J6T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST72F324J6T6
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
ST72F324J6T6/TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
ST72324Bxx
Table 55.
Table 56.
1:0 SPR[1:0]
Bit
7
6
5
4
3
2
MSTR
Name
CPOL
CPHA
SPR2
SPIE
SPE
SPICR register description
SPI master mode SCK frequency
Serial clock
Serial Peripheral Interrupt Enable
Serial Peripheral Output Enable
Divider Enable
Master mode
Clock Polarity
Clock Phase
Serial clock frequency
This bit is set and cleared by software.
0: Interrupt is inhibited.
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
These bits are set and cleared by software. Used with the SPR2 bit, they select
the baud rate of the SPI serial clock SCK output by the SPI in master mode
(seeTable
Note: These 2 bits have no effect in slave mode.
f
f
CPU
CPU
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56).
Master mode fault (MODF) on page
Master mode fault (MODF) on page
SPR2
Function
1
0
Table 56: SPI master mode SCK
SPR1
0
0
On-chip peripherals
102). The SPE bit
102).
SPR0
0
0
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